Patent Assignment
Reel/Frame 071692/0511
Change of Name
Recorded: 2025-06-23
Pages: 6
Assignor
GE INTELLECTUAL PROPERTY LICENSING, LLC
Executed: 2024-08-19
Assignee
DOLBY INTELLECTUAL PROPERTY LICENSING, LLC
1 RESEARCH CIRCLE, NISKAYUNA, NEW YORK, 12309
Covered Properties
(63)
Non-Magnetic Package and Method of Manufacture
PCT:
PCT/US2015/057517 ↗
Lid and Method for Sealing a Non-Magnetic Package
PCT:
PCT/US2015/057534 ↗
Rf Micro-Electromechanical Systems Having Inverted Microstrip Transmission Lines and Method of Making
PCT:
PCT/US2016/042706 ↗
Electronics Package Having a Multi-Thickness Conductor Layer and Method of Manufacturing Thereof
PCT:
PCT/US2017/057625 ↗
Electronics Package Having a Self-Aligning Interconnect Assembly and Method of Making Same
PCT:
PCT/US2018/039464 ↗
Semiconductor Logic Device and System and Method of Embedded Packaging of Same
PCT:
PCT/US2018/058374 ↗
Semiconductor Logic Device and System and Method of Embedded Packaging of Same
PCT:
PCT/US2018/058380 ↗
Semiconductor Logic Device and System and Method of Embedded Packaging of Same
PCT:
PCT/US2018/058385 ↗
Semiconductor Logic Device and System and Method of Embedded Packaging of Same
PCT:
PCT/US2018/059352 ↗
Contact material, device including contact material, and method of making
Application:
11/480,812 →
Publication:
US 2006/0274470
Interconnect Structure
Application:
11/828,550 →
Publication:
US 2009/0028491
Electrical Connection Through a Substrate to a Microelectromechanical Device
System and Method of Forming a Low Profile Conformal Shield
System and Method of Forming a Wafer Scale Package
Demountable Interconnect Structure
Method of Making Demountable Interconnect Structure
Interconnect Structure Including Hybrid Frame Panel
Ultra Thin Die Electronic Package
System and Method for Pre-Patterned Embedded Chip Build-Up
System and Method of Forming a Patterned Conformal Structure
System and Method for Stacked Die Embedded Chip Build-Up
Stackable Electronic Package
Integrated Circuit Package and Method of Making Same
Application:
12/410,255 →
Publication:
US 2011/0156261
Stackable Electronic Package and Method of Fabricating Same
Integrated Circuit Package and Method of Making Same
System and Method of Forming Isolated Conformal Shielding Areas
Article Including Thermal Interface Element and Method of Preparation
Contact Material, Device Including Contact Material, and Method of Making
Stackable Electronic Package and Method of Fabricating Same
Interconnect Structure
3D Integrated Electronic Device Structure Including Increased Thermal Dissipation Capabilities
System and Method of Forming a Patterned Conformal Structure
Integrated Circuit Package and Method of Making Same
Application:
13/327,333 →
Publication:
US 2012/0171816
Ultrathin Buried Die Module and Method of Manufacturing Thereof
Stackable Electronic Package and Method of Fabricating Same
Heat Spreader with Flexible Tolerance Mechanism
Method of Fabricating a 3D Integrated Electronic Device Structure Including Increased Thermal Dissipation Capabilities
Ultrathin Buried Die Module and Method of Manufacturing Thereof
Interconnect Devices for Electronic Packaging Assemblies
Non-Magnetic Package and Method of Manufacture
Lid and Method for Sealing a Non-Magnetic Package
Radio Frequency Micro-Electromechanical Systems Having Inverted Microstrip Transmission Lines and Method of Making the Same
Embedded Dry Film Battery Module and Method of Manufacturing Thereof
Three-Dimensional Stacked Integrated Circuit Devices and Methods of Assembling the Same
Electronics Package Having a Multi-Thickness Conductor Layer and Method of Manufacturing Thereof
Heat Spreader with Flexible Tolerance Mechanism
Stackable Electronic Package and Method of Fabricating Same
Patent:
47,651 →
Application:
15/415,549 →
Radio Frequency Die Package with Inverted Ground Plane and Method of Making Same
Method for Making a Seam-Sealable Non-Magnetic Lid and Package
Electronics Package Having a Self-Aligning Interconnect Assembly and Method of Making Same
Patent:
10,163,773 →
Application:
15/675,144 →
Semiconductor Logic Device and System and Method of Embedded Packaging of Same
Patent:
10,211,141 →
Application:
15/816,254 →
Semiconductor Logic Device and System and Method of Embedded Packaging of Same
Semiconductor Logic Device and System and Method of Embedded Packaging of Same
Semiconductor Logic Device and System and Method of Embedded Packaging of Same
Interconnect Devices for Electronic Packaging Assemblies
Patent:
48,015 →
Application:
15/886,478 →
Stackable Electronic Package and Method of Fabricating Same
Electronics Package Having a Multi-Thickness Conductor Layer and Method of Manufacturing Thereof
Device Almost Last Embedded Device Structure and Method of Manufacturing Thereof
Patent:
10,504,826 →
Application:
16/153,892 →
Multilayer Interconnect Structure with Buried Conductive via Connections and Method of Manufacturing Thereof
Electronics Package for Light Emitting Semiconductor Devices and Method of Manufacturing Thereof
Non-Magnetic Package and Method of Manufacture
Electronics Package Having a Self-Aligning Interconnect Assembly and Method of Making Same
Heat Spreader with Flexible Tolerance Mechanism
Application:
61/733,138 →
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.