Method of fabricating a 3D integrated electronic device structure including increased thermal dissipation capabilities

1. A method comprising:

providing a three-dimensional (3D) integrated chip assembly, the method of providing the chip assembly comprising;

providing a device substrate having a first main surface and a second main surface, the device substrate including a plurality of input/output connections on at least one of the first main surface and the second main surface;

disposing a MEMS relay comprising one or more heat generating elements on the device substrate;

bonding a cap layer to the device substrate, the cap layer having a first main surface and a second main surface;

disposing a sealing ring about the MEMS relay;

forming a hermetic seal about the MEMS relay, the hermetic seal at least partially defined by the device substrate, the cap layer and the sealing ring and wherein the sealing ring is not in electrical communication with the MEMS relay and the device substrate; and

providing a substrate including a plurality of input/output connections; and

flip chip bonding the three-dimensional (3D) integrated chip assembly to the substrate to form an apparatus,

wherein the apparatus provides a plurality of electrically and thermally conductive paths through the three-dimensional (3D) integrated chip assembly to dissipate heat generated within the apparatus and provide electrical connections to the MEMS relay.

2. The method as claimed in claim 1 , further comprising positioning a heat spreader proximate the three-dimensional (3D) integrated chip assembly via a thermal interface material (TIM) for facilitating dissipation of heat from the apparatus.

3. The method as claimed in claim 1 , wherein the cap layer further comprises a plurality of through wafer vias formed therein and a plurality of first input/output contacts disposed over a first main surface thereof and a plurality of second input/output contacts disposed over a second main surface thereof, wherein the plurality of second input/output contacts are electrically connected to the plurality of first input/output contacts through the plurality of through wafer vias.

4. The method as claimed in claim 3 , wherein the plurality of first input/output contacts disposed over the first main surface of the cap layer facilitate coupling to a plurality of input/output pads of the substrate to which the cap layer is to be attached, and

wherein the plurality of second input/output contacts disposed over the second main surface of the cap layer facilitate coupling to a plurality of input/output contacts of the device substrate to which the cap layer is also to be attached.

5. The method as claimed in claim 1 , wherein the device substrate further comprises a plurality of through wafer vias formed therein and a plurality of first input/output contacts disposed over a first main surface thereof, wherein the plurality of first input/output contacts are electrically connected to the MEMS relay through the plurality of through wafer vias.

6. The method as claimed in claim 5 , wherein the plurality of first input/output contacts disposed over the first main surface of the device substrate facilitate coupling to a plurality of input/output pads of a substrate to which the device substrate is to be attached, and

wherein a plurality of thermally conductive traces disposed over the second main surface of the device substrate facilitate coupling of the MEMS relay to the device substrate.

7. A method comprising:

providing a three-dimensional (3D) integrated chip assembly comprising;

providing a device substrate including a MEMS relay comprising one or more integrated circuits disposed on the device substrate;

bonding a cap layer to the device substrate, the cap layer comprising a semiconductor material;

disposing a sealing ring about the MEMS relay;

forming a hermetic seal about the MEMS relay, the hermetic seal at least partially defined by the device substrate, the cap layer and the sealing ring and wherein the hermetic seal is not in electrical communication with the MEMS relay;

flip chip bonding the three-dimensional (3D) integrated chip assembly to a substrate to form an apparatus; and

positioning a heat spreader proximate the three-dimensional (3D) integrated chip assembly via a thermal interface material (TIM) for facilitating dissipation of heat from the apparatus,

wherein the apparatus provides a plurality of electrically and thermally conductive paths through the three-dimensional (3D) integrated chip assembly to dissipate heat generated within the apparatus and provide electrical connections to the MEMS relay.

8. The method as claimed in claim 7 , wherein the cap layer further comprises a plurality of through wafer vias formed therein and a plurality of first input/output contacts disposed over a first main surface thereof and plurality of second input/output contacts disposed over a second main surface thereof, wherein the plurality of second input/output contacts are electrically connected to the plurality of first input/output contacts through the plurality of through wafer vias, and

wherein the plurality of first input/output contacts disposed over the first main surface of the cap layer facilitate coupling to a plurality of input/output pads of the substrate to which the cap layer is to be attached, and

wherein the plurality of second input/output contacts disposed over the second main surface of the cap layer facilitate coupling to a plurality of input/output contacts of the device substrate to which the cap layer is also to be attached.

9. The method as claimed in claim 7 , wherein the device substrate further comprises a plurality of through wafer vias formed therein and a plurality of first input/output contacts disposed over a first main surface thereof, wherein the plurality of first input/output contacts are electrically connected to the MEMS relay through the plurality of through wafer vias and a plurality of thermally conductive traces, and wherein the plurality of first input/output contacts disposed over the first main surface of the device substrate facilitate coupling to a plurality of input/output pads of the substrate to which the device substrate is to be attached.

10. The method as claimed in claim 7 , wherein the substrate is one of a printed circuit board (PCB) or a flexible substrate.

11. The method as claimed in claim 7 , wherein the substrate is comprised of a semiconductor material and the cap layer is comprised of a semiconductor material that matches at least in part the semiconductor material of the substrate.

12. The method as claimed in claim 7 , wherein the device substrate is an active device layer.

13. A method comprising:

providing a MEMS relay device including a cap layer, a device substrate, a sealing ring and a hermetic seal formed about the MEMS relay and at least partially defined by the cap layer, the device substrate and the sealing ring and wherein the sealing ring is not in electrical communication with the MEMS relay device and the device substrate; and

providing a substrate;

flip chip bonding the MEMS relay device to the substrate.

14. The method as claimed in claim 13 , wherein the cap layer further comprises a plurality of through wafer vias formed therein and a plurality of first input/output contacts disposed over a first main surface thereof and plurality of second input/output contacts disposed over a second main surface thereof, wherein the plurality of second input/output contacts are electrically connected to the plurality of first input/output contacts through the plurality of through wafer vias, and

wherein the plurality of first input/output contacts disposed over the first main surface of the cap layer facilitate coupling to a plurality of input/output pads of the substrate to which the cap layer is to be attached, and

wherein the plurality of second input/output contacts disposed over the second main surface of the cap layer facilitate coupling to a plurality of input/output contacts of the device substrate to which the cap layer is also to be attached.

15. The method as claimed in claim 13 , wherein the device substrate further comprises a plurality of through wafer vias formed therein and a plurality of first input/output contacts disposed over a first main surface thereof, wherein the plurality of first input/output contacts are electrically connected to the MEMS relay through the plurality of through wafer vias and a plurality of thermally conductive trace, and wherein the plurality of first input/output contacts disposed over the first main surface of the device substrate facilitate coupling to a plurality of input/output pads of the substrate to which the device substrate is to be attached.