IP Library › Granted Patent US 8,457,213
Granted Patent B2
US 8,457,213 · App. 12/470,151 · Granted Jun 4, 2013

Video system and scaler

Inventors: Jin-Sheng Gong (Hsinchu, TW); Wei-Lun Weng (Banciao, TW); Yu-Pin Lin (Changjhih Township, TW)
Assignee: Realtek Semiconductor Corp.
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Quick Facts
Patent No.
US 8,457,213
App. No.
12/470,151
Granted
Jun 4, 2013
Kind
B2
Abstract

A video system includes a decoder and a scaler. The decoder tracks a video signal, generates a synchronization signal and a frequency offset signal, decodes the video signal, and outputs a decoded signal in accordance with the synchronization signal. The scaler generates a frequency control signal in accordance with the frequency drift signal, generates an output clock signal in accordance with the frequency control signal, generates a scaled signal in accordance with the decoded signal, and outputs a display signal in accordance with the scaled signal and the output clock signal.

Claims (59)

1. A video system comprising:

a first decoder including

a first tracking unit, tracking a first video signal to generate a first synchronization signal and a first frequency offset signal, and

a first decoding unit, decoding the first video signal and outputting a first decoded signal in accordance with the first synchronization signal; and

a scaler including

a frequency control unit, receiving the first frequency offset signal and generating a frequency control signal,

a clock generating unit, generating an output clock signal in accordance with the frequency control signal,

a scaling circuit, receiving the first decoded signal and generating a scaled signal, and

an output unit, receiving the scaled signal and the output clock signal and outputting a display signal.

2. The video system as claimed in claim 1 , wherein the first frequency offset signal indicates a frequency variation of the first synchronization signal.

3. The video system as claimed in claim 1 , wherein the frequency control unit includes a low pass filter.

4. The video system as claimed in claim 1 , further comprising:

a second decoder, generating a second decoded signal, a second synchronization signal, and a second frequency offset signal in accordance with a second video signal;

wherein the frequency control unit selects one of the first and second frequency offset signals in accordance with a mode selection signal to generate the frequency control signal; and

wherein the scaling circuit selects one of the first and second decoded signals in accordance with the mode selection signal and scales the selected one of the first and second decoded signals to generate the scaled signal.

5. The video system as claimed in claim 4 , wherein the frequency control unit includes a multiplexing unit for selecting the one of the first and second frequency offset signals, and a low pass filter filtering the selected one of the first and second frequency offset signals.

6. The video system as claimed in claim 5 , wherein filtering parameters of the low pass filter are fixed.

7. The video system as claimed in claim 5 , wherein the low pass filter is an adjustable low pass filter having filtering parameters adjusted according to the mode selection signal.

8. The video system as claimed in claim 4 , wherein the scaling circuit includes a multiplexing unit selecting one of the first and second decoded signals, and a scaling unit scaling the selected one of the first and second decoded signals.

9. The video system as claimed in claim 4 , wherein the first decoder is a component video signal decoder, and the second decoder is a High Definition Multimedia Interface decoder.

10. The video system as claimed in claim 1 , wherein the frequency control unit utilizes an open-loop mechanism to generate the frequency control signal.

11. The video system as claimed in claim 1 , wherein the frequency control unit includes a first multiplexing unit, and the scaling circuit includes a second multiplexing unit and a scaling unit, the first and second multiplexing units being simultaneously controlled through a mode selection signal.

12. A scaler comprising:

a frequency control unit, receiving a frequency offset signal and generating a frequency control signal;

a clock generating unit coupled to the frequency control unit and generating an output clock signal in accordance with the frequency control signal;

a scaling circuit, receiving a decoded signal and generating a scaled signal; and

an output unit, coupled to the clock generating unit and the scaling circuit, receiving the scaled signal and the output clock signal and outputting a display signal.

13. The scaler as claimed in claim 12 , wherein the frequency offset signal indicates a frequency variation of a synchronization signal corresponding to the decoded signal.

14. The scaler as claimed in claim 12 , wherein the frequency control unit includes a low pass filter.

15. The scaler as claimed in claim 12 , wherein the frequency control unit includes an adjustable low pass filter having filtering parameters adjusted in accordance with a mode selection signal.

16. The scaler as claimed in claim 12 , wherein the frequency control unit includes a first multiplexing unit, and the scaling circuit includes a second multiplexing unit and a scaling unit, the first and second multiplexing units being simultaneously controlled through a mode selection signal.

17. The scaler as claimed in claim 12 , wherein the frequency control unit utilizes an open-loop mechanism to generate the frequency control signal.

18. A video system comprising:

a first decoder including

a first tracking unit, tracking a first video signal to generate a first synchronization signal, and

a first decoding unit, decoding the first video signal and outputting a first decoded signal in accordance with the first synchronization signal; and

a scaler including

a frequency control unit, receiving the first synchronization signal and generating a frequency control signal,

a clock generating unit, generating an output clock signal in accordance with the frequency control signal,

a scaling circuit, receiving the first decoded signal and generating a scaled signal, and

an output unit, receiving the scaled signal and the output clock signal and outputting a display signal.

19. The video system as claimed in claim 18 , wherein the frequency control unit includes:

a counter, counting the first synchronization signal in accordance with a reference clock to generate a count value; and

a delta calculator, calculating the frequency control signal according to the count value and a predetermined period.

20. The video system as claimed in claim 18 , further comprising:

a second decoder, generating a second decoded signal and a second synchronization signal in accordance with a second video signal;

wherein the frequency control unit selects one of the first and second synchronization signals in accordance with a mode selection signal, and tracks the selected one of the first and second synchronization signals to generate the frequency control signal; and

wherein the scaling circuit selects one of the first and second decoded signals in accordance with the mode selection signal, and scales the selected one of the first and second decoded signals to generate the scaled signal.

21. The video system as claimed in claim 18 , wherein the frequency control unit includes a first multiplexing unit, and the scaling circuit includes a second multiplexing unit and a scaling unit, the first and second multiplexing units being simultaneously controlled through a mode selection signal.

22. The video system as claimed in claim 20 , wherein the first decoder is a component video signal decoder, and the second decoder is a High Definition Multimedia Interface decoder.

23. A scaler comprising:

a frequency control unit, receiving a synchronization signal corresponding to a decoded signal and generating a frequency control signal;

a clock generating unit, coupled to the frequency control unit and outputting an output clock signal in accordance with the frequency control signal;

a scaling circuit, receiving the decoded signal and generating a scaled signal; and

an output unit, coupled to the clock generating unit and the scaling circuit, receiving the scaled signal and the output clock signal and outputting a display signal.

24. The scaler as claimed in claim 23 , wherein the frequency control unit includes:

a counter, counting the synchronization signal in accordance with a reference clock to generate a count value; and

a delta calculator, calculating the frequency control signal according to the count value and a predetermined period.

25. The scaler as claimed in claim 23 , wherein the frequency control unit includes a first multiplexing unit, and the scaling circuit includes a second multiplexing unit and a scaling unit, the first and second multiplexing units being simultaneously controlled through a mode selection signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2009
From: GONG, JIN-SHENG; WENG, WEI-LUN; LIN, YU-PIN
To: REALTEK SEMICONDUCTOR CORP.
Reel/Frame 022721/0607 →
Priority Claims (1)
TW 97119354 A · May 26, 2008 · national
Continuity (1)
Related Publication 20090290646A1 · Nov 26, 2009