IP Library Granted Patent US 8,558,836
Granted Patent B2
US 8,558,836 · App. 12/476,161 · Granted Oct 15, 2013

Scalable and unified compute system

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Quick Facts
Patent No.
US 8,558,836
App. No.
12/476,161
Granted
Oct 15, 2013
Kind
B2
Abstract

A Scalable and Unified Compute System performs scalable, repairable general purpose and graphics shading operations, memory load/store operations and texture filtering. A Scalable and Unified Compute. Unit Module comprises a shader pipe array, a texture mapping unit, and a level one texture cache system. It accepts ALU instructions, input/output instructions, and texture or memory requests for a specified set of pixels, vertices, primitives, surfaces, or general compute work items from a shader program and performs associated operations to compute the programmed output data. The texture mapping unit accepts source data addresses and instruction constants in order to fetch, format, and perform instructed filtering interpolations to generate formatted results based on the specific corresponding data stored in a level one texture cache system. The texture mapping unit consists of an address generating system, a pre-formatter module, interpolator module, accumulator module and a format module.

Claims (78)

1. An apparatus, comprising:

a hardware-based shader pipe array configured to accept texture instructions for a specified set of pixels, vertices, primitives, surfaces, or compute work items and to generate output data;

a hardware-based level one texture cache system configured to store the texture output data; and

a hardware-based texture mapping unit configured to:

retrieve texture output data from the level one texture cache system and generate formatted accumulated interpolation data, wherein

the texture mapping unit further comprises:

a pre-formatter module configured to accept texel data and generate normalized fixed point texel data;

an interpolator module configured to perform an interpolation on the normalized fixed point texel data from the pre-formatter module and generate re-normalized floating point texel data;

an accumulator module configured to accumulate floating point texel data from the interpolator module; and

a format module configured to convert texel data from the accumulator module into a standard floating point representation.

2. The apparatus of claim 1 , wherein the shader pipe array is configured to accept ALU, load/store, and output instructions.

3. The apparatus of claim 1 , further comprising a redundant shader pipe array configured to process shader pipe data destined for a defective shader pipe of the shader pipe array.

4. The apparatus of claim 1 , wherein the shader pipe array comprises a shader pipe block.

5. The apparatus of claim 4 , wherein the shader pipe block is configured to contain one or more shader pipes.

6. The apparatus of claim 1 , wherein the level one texture cache system is configured to read and write to a level two cache system.

7. The apparatus of claim 1 , wherein the interpolator module is configured to perform one or more interpolations in order to achieve at least one of:

a bilinear texture filtering;

a trilinear texture filtering; and

an anisotropic texture filtering.

8. A method for computing, comprising:

receiving, using a processor, a set of texture requests for a specified set of pixels, vertices, primitives, surfaces, or compute work items;

generating, using the processor, a data set of addresses based on a shader program instruction for the specified set of pixels, vertices, primitives, surfaces, or compute work items;

retrieving, using the processor, stored texel data from a level one cache system; and

calculating, using the processor, a formatted accumulated interpolation based on the retrieved texel data and an originating shader instruction, further comprising:

receiving floating point texel data;

generating normalized fixed point texel data from the floating point texel data;

performing an interpolation on the normalized fixed point texel data;

generating re-normalized floating point texel data;

accumulating re-normalized texel data; and

formatting the accumulated re-normalized texel data into a standard floating point representation.

9. The computing method of claim 8 , further comprising:

processing shader pipe data destined for a defective shader pipe.

10. The computing method of claim 8 , further comprising:

reading from and writing to a level two cache system from the level one texture cache system.

11. The computing method of claim 8 , wherein the interpolation further comprises:

bilinear texture filtering;

trilinear texture filtering; and

anisotropic texture filtering.

12. The computing method of claim 8 , wherein the method is performed by synthesizing hardware description language instructions.

13. A system for computing system, comprising:

a processor; and

a memory, in communication with the processor, configured to store a plurality of processing instructions for directing a computing system to:

receive a set of texture requests for a specified set of pixels, vertices, primitives, surfaces, or compute work items;

generate a data set of addresses based on a shader program instruction for the specified set of pixels, vertices, primitives, surfaces, or compute work items;

retrieve stored texel data from a level one cache system; and

calculate a formatted accumulated interpolation based on the retrieved texel data and an originating shader instruction, further comprising instructions for causing the computing system to:

receive floating point texel data;

generate normalized fixed point texel data from the floating point texel data;

perform an interpolation on the normalized fixed point texel data;

generate re-normalized floating point texel data;

accumulate re-normalized texel data; and

format the accumulated re-normalized texel data into a standard floating point representation.

14. The computing system of claim 13 , further comprising instructions for causing the computing system to:

process shader pipe data destined to a defective shader pipe.

15. The computing system of claim 13 , further comprising instructions for causing the computing system to:

read and write to a level two cache system from the level one texture cache system.

16. The computing system of claim 13 , further comprising instructions for causing the computing system to:

filter with a bilinear texture filter;

filter with a trilinear texture filter; and

filter with an anisotropic texture filter.

17. A non-transitory computer readable storage medium carrying one or more sequences of one or more instructions execution of which by one or more processor-based computing devices cause the one or more computing devices to perform a method of computing, the method performing operations comprising:

receiving a set of texture requests for a specified set of pixels, vertices, primitives, surfaces, or compute work items;

generating a data set of addresses based on a shader program instruction for the specified set of pixels, vertices, primitives, surfaces, or compute work items;

retrieving stored texel data from a level one cache system; and

calculating a formatted accumulated interpolation based on the retrieved texel data and; an originating shader instruction, further comprising:

receiving floating point texel data;

generating normalized fixed point texel data from the floating point texel data;

performing an interpolation on the normalized fixed point texel data generating re-normalized floating point texel data;

accumulating re-normalized texel data; and

formatting the accumulated re-normalized texel data into a standard floating point representation.

18. The non-transitory computer readable storage medium of claim 17 , further comprising:

reading from and writing to a level two cache system from the level one texture cache system.

19. The non-transitory computer readable storage medium of claim 17 , further comprising:

bilinear texture filtering;

trilinear texture filtering; and

anisotropic texture filtering.

20. The non-transitory computer readable storage medium of claim 17 , further comprising;

processing shader pipe data destined for a defective shader pipe.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2025
From: ONESTA IP LLC
To: MAGNUSON RESEARCH LLC
Reel/Frame 071352/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2024
From: ADVANCED MICRO DEVICES, INC.
To: ONESTA IP, LLC
Reel/Frame 069381/0951 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2009
From: MANTOR, MICHAEL J.; BRADY, JEFFREY T.; FOWLER, MARK C.; ZINI, MARCOS P.
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 023037/0936 →