High-density nonvolatile memory
View Patent ↗Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.
1. A monolithic three dimensional memory array comprising:
a plurality of substantially parallel first conductors above a substrate, the first conductors not comprising monocrystalline silicon;
a plurality of first semiconductor elements above the first conductors, each first semiconductor element comprising a first heavily doped layer of a first conductivity type, a second lightly doped layer, and a third heavily doped layer of a second conductivity type;
a plurality of first antifuse layers, each first antifuse layer formed above one of the plurality of first semiconductor elements; and
a plurality of substantially parallel second conductors, the second conductors above the plurality of first antifuse layers.
2. The monolithic three dimensional memory array of claim 1 , wherein the substrate comprises monocrystalline silicon.
3. The monolithic three dimensional memory array of claim 1 , wherein the first conductors or the second conductors comprise tungsten.
4. The monolithic three dimensional memory array of claim 1 , wherein the first semiconductor elements are vertically oriented pillars.
5. The monolithic three dimensional memory array of claim 1 , wherein the first semiconductor elements comprise polycrystalline silicon.
6. The monolithic three dimensional memory array of claim 1 , wherein the first antifuse layers comprise an oxide.
7. The monolithic three dimensional memory array of claim 6 , wherein the oxide comprises silicon dioxide.
8. The monolithic three dimensional memory array of claim 1 , further comprising a plurality of second semiconductor elements above the plurality of substantially parallel second conductors.
9. The monolithic three dimensional memory array of claim 8 , further comprising a plurality of third conductors formed above the plurality of second semiconductor elements.
10. The monolithic three dimensional memory array of claim 1 , further comprising a plurality of memory cells, each memory cell comprising a portion of one of the first conductors, one of the first semiconductor elements, and a portion of one of the second conductors.
11. The monolithic three dimensional memory array of claim 1 , wherein the first conductors extend in a first direction, and the second conductors extend in a second direction, the second direction different from the first direction.
12. The monolithic three dimensional memory array of claim 11 , wherein the second direction is substantially perpendicular to the first direction.
13. The monolithic three dimensional memory array of claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type.
14. The monolithic three dimensional memory array of claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.
15. The monolithic three dimensional memory array of claim 1 , wherein each third heavily doped layer is doped by ion implantation.
16. The monolithic three dimensional memory array of claim 1 , wherein each first heavily doped layer is doped by in situ doping.