Method for manufacturing capacitor of semiconductor device

1. A method comprising:

forming a lower metal layer over a substrate;

forming a dielectric layer over the lower metal layer;

forming an upper metal layer over the dielectric layer;

forming an upper electrode and a dielectric layer pattern by performing a reactive ion etching process with respect to the upper metal layer using the dielectric layer as an etch stop layer, and exposing a top surface of the lower metal layer; and

performing a chemical down-stream etch process to remove a by-product of a sidewall of the upper electrode.

2. The method of claim 1 , including forming a lower electrode by performing a reactive ion etching process with respect to the lower metal layer after the chemical down-stream etch process has been performed.

3. The method of claim 1 , wherein a second dielectric layer includes at least one selected from the group consisting of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ) and tantalum oxide (Ta 2 O 5 ).

4. The method of claim 1 , wherein first and second dielectric layers include aluminum oxide (Al 2 O 3 ).

5. The method of claim 1 , wherein a total thickness of first to third dielectric layers is in a range of about 1 Å to about 300 Å.

6. The method of claim 1 , wherein the chemical down-stream etch process is performed under conditions of RF power of about 600 W to about 800 W, pressure of about 1 Pa to about 100 Pa, an O 2 flow rate of about 5 sccm to about 400 sccm, a CF 4 flow rate of about 300 sccm to about 500 sccm, a N 2 flow rate of about 50 sccm to about 300 sccm, and process time of about 40 seconds to about 400 seconds.

7. The method of claim 1 , including forming a barrier metal layer over the lower metal layer.

8. The method of claim 7 , including forming a barrier metal layer over the dielectric layer.

9. The method of claim 8 , wherein the upper and lower metal layers are formed using copper.

10. A method comprising:

forming a lower metal layer over a substrate;

forming a first dielectric layer over the lower metal layer;

forming a second dielectric layer over the first dielectric layer;

forming a third dielectric layer over the second dielectric layer;

forming an upper metal layer over the third dielectric layer;

forming an upper electrode and first to third dielectric layer patterns by performing a reactive ion etching process with respect to the upper metal layer using the first to third dielectric layers as an etch stop layer, and exposing a top surface of the lower metal layer; and

performing a chemical down-stream etch process to remove a by-product of a sidewall of the upper electrode.

11. The method of claim 10 , wherein the first and third dielectric layers are formed by depositing Al 2 O 3 using trimethylaluminum and ozone (O 3 ).

12. The method of claim 10 , wherein the second dielectric layer is formed by depositing HfO 2 using tetrakis[ethylmethylamino]hafnium and O 3 .

13. The method of claim 10 , wherein the second dielectric layer includes at least one selected from the group consisting of HfO 2 , ZrO 2 and Ta 2 O 5 , and the first and third dielectric layers include Al 2 O 3 .

14. The method of claim 10 , wherein the capacitor having the dielectric layer has capacitance in a range of about 8 fF/μ 2 to about 10 fF/μ 2 .

15. The method of claim 10 , wherein the CDE process is performed under conditions of RF power of about 600 W to about 800 W, pressure of about 1 Pa to about 100 Pa, an O 2 flow rate of about 5 sccm to about 400 sccm, a CF 4 flow rate of about 300 sccm to about 500 sccm, a N 2 flow rate of about 50 sccm to about 300 sccm, and process time of about 40 seconds to about 400 seconds.

16. The method of claim 10 , wherein the first and third dielectric layers are formed by depositing Al 2 O 3 through an automatic layer deposition scheme by using trimethylaluminum and ozone (O 3 ).

17. The method of claim 10 , wherein the second dielectric layer is formed by depositing HfO2 through an automatic layer deposition scheme by using tetrakis[ethylmethylamino]hafnium and O 3 .

18. The method of claim 10 , wherein a thickness of the first dielectric layer is in a range of about 30 ű2 Å, a thickness of the second dielectric layer is in a range of about 100 ű5 Å, and a thickness of the third dielectric layer is a range of about 30 ű2 Å.

19. The method of claim 10 , including forming a barrier metal layer over the lower metal layer.

20. The method of claim 19 , including forming a barrier metal layer over the dielectric layer.