Through-hole layout apparatus that reduces differences in layout density of through-holes

1. A through-hole layout apparatus comprising:

an extractor, implemented by a processor, configured to extract a plurality of through-holes interconnecting an upper layer wiring and a lower layer wiring from design data for a semiconductor integrated circuit;

a calculator, implemented by the processor, configured to calculate, for each of the plurality of through-holes extracted by said extractor, a layout density of through-holes in a corresponding predetermined region centered on each of said though-holes, respectively;

a selector, implemented by the processor, configured to select a target through-hole among said plurality through-holes extracted by the extractor, where said layout density calculated by said calculator for the target through-hole is lower than a predetermined value; and

a through-hole adder, implemented by the processor, configured to determine, for the target through-hole selected by the selector, a first given position in the corresponding predetermined region centered on said target through-hole as a placement position at which a through-hole is to be added and adding a through-hole at said placement position on said design data.

2. The through-hole layout apparatus according to claim 1 , wherein said first given position in said predetermined region is at a predetermined distance from said target through-hole in a predetermined direction in said predetermined region, is on an upper layer wiring that is connected to said target through-hole, and is a position where no through-hole is placed.

3. The through-hole layout apparatus according to claim 2 , wherein if there is room for extending an lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, said through-hole adder extends said lower layer wiring to said position corresponding to said placement position and adds a through-hole interconnecting said upper layer wiring and said lower layer wiring at said placement position on said design data.

4. The through-hole layout apparatus according to claim 2 , wherein if there is no room for extending an lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, said through-hole adder places an interlayer wiring at a position corresponding to said placement position between said upper layer wiring and said lower layer wiring and adds a through-hole interconnecting said upper layer wiring and said interlayer wiring at said placement position on said design data.

5. The through-hole layout apparatus according to claim 1 , wherein:

said extractor extracts a plurality of through-holes from processed design data to which a through-hole has been added by said through-hole adder;

said calculator calculates, for each of the plurality of through-holes extracted by said extractor, excluding the through-hole added by said through-hole adder, the layout density of through-holes in the corresponding predetermined region centered on each of said though-holes, respectively;

said selector selects a target through-hole among the plurality of through-holes, excluding said through-holes added by said through-hole adder, where said layout density calculated by said calculator for the target through hole is lower than the predetermined value; and

said through-hole adder determines, for the target through-hole selected by said selector, a second given position in the predetermined region centered on said target through-hole as a placement position at which a through-hole is to be added and adds a through-hole at said placement position on said processed design data.

6. The through-hole layout apparatus according to claim 5 , wherein said second given position in said predetermined region is a position at said predetermined distance from said target through-hole at said predetermined direction in said predetermined region and is a position where there is room for extending an upper layer wiring that is connected to said target through-hole, or a position which is on an upper layer wiring adjacent to said upper layer wiring and at which no through-hole is placed.

7. The through-hole layout apparatus according to claim 6 , wherein if said placement position is a position at which there is room for extending said upper layer wiring that is connected to said target through-hole, said through-hole adder extends said upper layer wiring to said placement position and, if there is room for extending a lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, extends said lower layer wiring to said position corresponding to said placement position and adds a through-hole interconnecting said upper layer wiring and said lower layer wiring at said placement position on said processed design data.

8. The through-hole layout apparatus according to claim 6 , wherein if said placement position is a position at which there is room for extending said upper layer wiring that is connected to said target through-hole, said through-hole adder extends said upper layer wiring to said placement position and, if there is no room for extending a lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, places an interlayer wiring at a position corresponding to said placement position between said upper layer wiring and said lower layer wiring and adds a through-hole interconnecting said upper layer wiring and said interlayer wiring at said placement position on said processed design data.

9. The through-hole layout apparatus according to claim 6 , wherein if said placement position is on said adjacent upper layer wiring and is a position where no through-hole is placed, said through-hole adder places an interlayer wiring at a position corresponding to said placement position between said upper layer wiring and said interlayer wiring and adds a through-hole interconnecting said upper layer wiring and said lower layer wiring at said placement position on said processed design data.

10. A through-hole layout method performed by a through-hole layout apparatus, comprising:

extracting, by a processor, a plurality of through-holes interconnecting an upper layer wiring and a lower layer wiring from design data for a semiconductor integrated circuit;

calculating, for each of the plurality of extracted through-holes, a layout density of through-holes in a corresponding predetermined region centered on each of said though-holes, respectively;

selecting a target through-hole among said plurality of through-holes where said calculated layout density for the target through-hole is lower than a predetermined value;

determining, for the selected target through-hole, a given position in the predetermined region centered on said target through-hole as a placement position at which a through-hole is to be added; and

adding a through-hole at said placement position on said design data.

11. The through-hole layout method according to claim 10 , wherein said first given position in said predetermined region is at a predetermined distance from said target through-hole in a predetermined direction in said predetermined region, is on an upper layer wiring that is connected to said target through-hole, and is a position where no through-hole is placed.

12. The through-hole layout method according to claim 11 , wherein, in adding a through-hole at said placement position, if there is room for extending an lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, said lower layer wiring is extended to a position corresponding to said placement position and a through-hole interconnecting said upper layer wiring and said lower layer wiring is added at said placement position on said design data.

13. The through-hole layout method according to claim 11 , wherein, in adding a through-hole at said placement position, if there is no room for extending an lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, an interlayer wiring is placed at a position corresponding to said placement position between said upper layer wiring and said lower layer wiring and a through-hole interconnecting said upper layer wiring and said interlayer wiring is added at said placement position on said design data.

14. The through-hole layout method according to claim 10 , wherein, in adding a through-hole in said placement position,

re-extraction is performed to extract a plurality of through-holes from processed design data to which a through-hole has been added;

recalculation is performed to calculate, for each of said plurality of through-holes extracted by said re-extraction excluding said through-hole added to said placement position, a layout density of through-holes in corresponding predetermined region centered on each of said though-holes, respectively;

re-selection is performed to select a target through-hole among said plurality of through-holes where said layout density calculated by said recalculation is lower than a predetermined value; and

re-addition is performed by determining, for each target through-hole selected by said reselection, a second given position in a predetermined region centered on said target through-hole as a placement position at which a through-hole is to be added and adding a through-hole at said placement position on the processed design data.

15. The through-hole layout method according to claim 14 , wherein said second given position in said predetermined region is a position at said predetermined distance from said target through-hole at said predetermined direction in said predetermined region and is a position where there is room for extending an upper layer wiring that is connected to said target through-hole, or a position which is on an upper layer wiring adjacent to said upper layer wiring and at which no through-hole is placed.

16. The through-hole layout method according to claim 15 , wherein in performing said re-addition, if said placement position is a position at which there is room for extending said upper layer wiring that is connected to said target through-hole, said upper layer wiring is extended to said placement position and, if there is room for extending a lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, said lower layer wiring is extended to said position corresponding to said placement position and a through-hole interconnecting said upper layer wiring and said lower layer wiring is added at said placement position on said processed design data.

17. The through-hole layout method according to claim 15 , wherein in performing said re-addition, if said placement position is a position at which there is room for extending said upper layer wiring that is connected to said target through-hole, said upper layer wiring is extended to said placement position and, if there is no room for extending a lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, an interlayer wiring is placed at a position corresponding to said placement position between said upper layer wiring and said lower layer wiring and a through-hole interconnecting said upper layer wiring and said interlayer wiring is added at said placement position on said processed design data.

18. The through-hole layout method according to claim 15 , wherein in performing said re-addition, if said placement position is on said adjacent upper layer wiring and is a position where no through-hole is placed, an interlayer wiring is placed at a position corresponding to said placement position between said upper layer wiring and said lower layer wiring and a through-hole interconnecting said upper layer wiring and said interlayer wiring is added at said placement position on said processed design data.

19. A method of forming a layout of a through-hole by a layout apparatus, comprising;

receiving a design data of a semiconductor circuit by the layout apparatus;

extracting, by a processor, a first through-hole and a second through-hole from the design data, the first through-hole including a first end connected to a first wiring at a first layer level extending in a first direction and a second end connected to a second wiring at a second layer level extending a second direction different from the first direction, the second through-hole including a first end connected to a third wiring at the first layer level extending in the first direction and a second end connected to a fourth wiring at the second layer level extending the second direction, a distance between the first wiring and a first adjacent wiring at the first layer level in the second direction adjacent to the first wiring, being larger than a distance between the third wiring and a second adjacent wiring at the first layer level in the second direction adjacent to the third wiring;

arranging, by the processor, a first additional through-hole adjacent to the first through-hole such that the first additional through-hole is arranged between the first through-hole and the first adjacent wiring, the first additional through-hole including a first end connected to an extended portion of the first wiring and a second end connected to the second wiring;

arranging, by the processor, a second additional through-hole adjacent to the second through-hole such that the second additional through-hole is arranged between the second through-hole and the second adjacent wiring, the second additional through-hole including a first end connected to a fifth wiring at a third layer level different from the first and second layer levels and a second end connected to the fourth wiring; and

outputting a design data of the semiconductor circuit which are added to the first and second additional through-holes.

20. The method as claimed in claim 19 , wherein the third layer level is positioned between the first and second layer levels.

21. The method as claimed in claim 20 , wherein the second wiring and the fourth wiring constitute a single wiring.

22. The method as claimed in claim 21 , further comprising:

arranging, by the through-hole adder, a third additional through-hole adjacent to the first through-hole such that the first through-hole is arranged between the third additional through-hole and the first additional through-hole, the third additional through-hole including a first end connected to a second extended portion of the first wiring and a second end connected to the second wiring; and

arranging, by the through-hole adder, a fourth additional through-hole adjacent to the second through-hole such that the second through-hole is arranged between the second additional through-hole and the fourth additional through-hole, the fourth additional through-hole including a first end connected to a sixth wiring at the third layer level and a second end connected to the fourth wiring.