Granted Patent B2

US 7,868,383 · App. 12/484,076 · Granted Jan 11, 2011

Abstract

Claims (23)

1. An integrated circuit (IC) device comprising:

a semiconductor substrate;

a plurality of device layers disposed one on top of another, the device layers comprising a base layer, one more alternating metal and dielectric layers, and a top layer;

a transistor formed in the base layer and having a gate;

a first contact formed in the top layer to receive a first supply voltage;

a second contact formed in the top layer to receive a second supply voltage;

a first continuity stack coupled between the gate of the transistor and the first contact and extending through the device layers, wherein the first continuity stack comprises a series connection of first continuity elements each formed in a corresponding one of the device layers; and

a second continuity stack coupled between the gate of the transistor and the second contact and extending through the device layers, wherein the second continuity stack comprises a series connection of second continuity elements each formed in a corresponding one of the device layers, and wherein the first and second continuity elements comprise connectivity structures.

2. The IC device of claim 1 , wherein:

in a first state, all the first continuity elements are conductive to electrically connect the gate to the first supply voltage and one or more of the second continuity elements are non-conductive to electrically isolate the gate from the second supply voltage; and

in a second state, all the second continuity elements are conductive to electrically connect the gate to the second supply voltage and one or more of the first continuity elements are non-conductive to electrically isolate the gate from the first supply voltage.

3. The IC device of claim 1 , wherein the first and second continuity stacks form a multi-level revision (MLR) cell for storing an output signal.

4. The IC device of claim 3 , wherein MLR cell selectively connects the gate of the transistor to either the first supply voltage or the second supply voltage.

5. The IC device of claim 3 , wherein the MLR cell does not consume static DC power.

6. The IC device of claim 3 , further including a plurality of MLR group structures, each comprising:

a plurality of the MLR cells, each assigned to a different one of the device layers; and

an encoder circuit having a plurality of inputs each coupled to the output of a corresponding MLR cell in the MLR group structure, and having an output to provide a corresponding one of a plurality of bits of a revision code.

7. The IC device of claim 6 , wherein each device layer is assigned to one MLR cell in each of the MLR group structures.

8. The IC device of claim 6 , wherein the revision code indicates design revisions in any of the device layers.

9. The IC device of claim 8 , wherein the revision codes are assigned to the design revisions in a non-sequential manner.

10. The IC device of claim 6 , wherein for each MLR group structure, the logic state of the corresponding bit of the revision code is controllable by any one of the MLR cell output signals in the MLR group structure.

11. The IC device of claim 6 , wherein the encoder circuit comprises a parity circuit that determines a parity of the MLR cell output signals for the corresponding MLR group structure.

12. The IC device of claim 11 , wherein the parity circuit comprises the transistor.

Assignments (9)