Use of emerging non-volatile memory elements with flash memory
View Patent ↗Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array.
1. A memory device comprising:
an array of transistor-based non-volatile memory elements; and
a circuit comprising sense circuitry coupled to the array, the sense circuitry comprising a data latch and a cache latch where each of the latches include emerging non-volatile memory elements and store data to be stored in the array and/or store data that was previously stored in the array.
2. The device of claim 1 , wherein the emerging non-volatile memory elements comprise phase change memory elements.
3. The device of claim 1 , wherein the emerging non-volatile memory elements comprise magnetoresistive memory elements.
4. The device of claim 1 , wherein the emerging non-volatile memory elements comprise resistive memory elements.
5. The device of claim 1 , wherein the emerging non-volatile memory elements comprise ferroelectric memory elements.
6. The device of claim 1 , wherein the emerging non-volatile memory elements comprise spin-transfer-torque memory elements.
7. The device of claim 1 , wherein the emerging non-volatile memory elements comprise nano-tube memory elements.
8. The device of claim 1 , wherein the array comprises a NAND flash memory and is organized into a plurality of pages having a page size, and wherein a number of the plurality of emerging non-volatile memory elements is equal to the page size.
9. The device of claim 1 , wherein the array comprises a NAND flash memory array and is organized into a plurality of blocks having a block size, and wherein the plurality of emerging non-volatile memory elements are organized into at least one block having the block size.
10. The device of claim 1 , wherein the array comprises a NAND flash memory array and is organized into a plurality of blocks having a block size, and wherein the plurality of emerging non-volatile memory elements are organized into more than one block having the block size.
11. A flash memory device comprising:
an array of transistor based non-volatile memory cells, the array being organized into a plurality of memory blocks, each memory block comprising a plurality of memory pages; and
a cache memory circuit electrically coupled to the array, the cache memory circuit comprising latches where the latches are a plurality of emerging non-volatile memory elements for storing data to be stored in the array, and the emerging non-volatile memory elements are organized into at least one memory block.
12. The flash memory device of claim 11 , wherein the array and the cache memory circuit are in a same module.
13. The flash memory device of claim 11 , wherein the array and the cache memory circuit are on a same circuit board.
14. The flash memory device of claim 11 , wherein the cache memory is stacked with the array in a same chip package.
15. The flash memory device of claim 11 , wherein the emerging non-volatile memory elements are organized into a plurality of memory blocks.
16. The flash memory device of claim 15 , wherein data stored in the memory blocks is error corrected before being programmed into a memory block in the array.
17. The flash memory device of claim 15 , wherein data stored in the memory blocks undergoes fragment fixing before being programmed into a memory block in the array.
18. The flash memory device of claim 15 , wherein at least one block of emerging non-volatile memory is used as a redundant block for a bad memory block in the array.
19. A method of operating a flash memory device comprising an array of transistor-based non-volatile memory elements and a circuit coupled to the array, the circuit comprising a plurality of emerging non-volatile memory elements, said method comprising:
storing data in at least one emerging non-volatile memory element;
copying the stored data into the array of flash memory cells during a programming operation;
mapping a bad memory block to a block of emerging non-volatile memory elements; and
copying the stored data into the block of emerging non-volatile memory elements.
20. The method of claim 19 , further comprising performing error correction on the stored data before copying the stored data into the array.
21. The method of claim 19 , further comprising performing fragment fixing on the stored data before copying the stored data into the array.
22. The method of claim 19 , wherein the stored data is trim information for the memory device.
23. The method of claim 19 , wherein the stored data is fuse information for the memory device.
24. The method of claim 19 , wherein the stored data is diagnostic data for the memory device.