Passive offset and overshoot cancellation for sampled-data circuits
A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase.
1. A switched-capacitor circuit with effective offset cancellation, comprising:
a level-crossing detector having an input terminal to determine when an input voltage crosses a predetermined voltage; a switched-capacitor network;
a waveform generator circuit comprising a ramp circuit, the waveform generator circuit operatively coupled to said switched-capacitor network, to apply a predetermined voltage waveform comprising segments of varying rates of change;
an offset capacitor operatively coupled between said level-crossing detector and said switched-capacitor network;
a first switch operatively coupled to said input terminal; and
an offset sampling capacitor operatively coupled to said first switch, said first switch connecting said offset sampling capacitor to said input terminal of said level-crossing detector during a first clock phase.
2. The switched-capacitor circuit as claimed in claim 1 , wherein said offset sampling capacitor is operatively coupled to a system common-mode voltage.
3. The switched-capacitor circuit as claimed in claim 1 , wherein said offset sampling capacitor is operatively coupled to ground.
4. The switched-capacitor circuit as claimed in claim 1 , wherein said waveform generator circuit includes a current source and a second switch.
5. The switched-capacitor circuit as claimed in claim 1 , wherein said predetermined voltage waveform is a ramp.
6. The switched-capacitor circuit as claimed in claim 1 , wherein said first clock phase is a charge transfer phase.
7. The circuit as claimed in claim 1 , wherein said waveform generator circuit comprises multiple outputs.
8. The circuit as claimed in claim 7 , wherein said multiple outputs of said ramp circuit are tri-stated during a second clock phase.
9. The switched-capacitor circuit as claimed in claim 8 , wherein said second clock phase is a sampling phase.
10. The circuit as claimed in claim 7 , wherein said ramp circuit includes a variable current source.
11. The circuit as claimed in claim 7 , wherein said ramp circuit includes a voltage bias source.
12. The circuit as claimed in claim 7 , wherein said ramp circuit includes a set of shorting switches.
13. The switched-capacitor circuit as claimed in claim 1 , wherein the level crossing by the level-crossing detector causes the voltage waveform to advance to a next segment.