Constant slope ramp circuits for sampled-data circuits
A circuit includes a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a predetermined voltage level. A first stage set of capacitors is operatively coupled to the level-crossing detector. A ramp circuit is operatively coupled to the set of series-connected capacitors. A second stage set of capacitors is operatively coupled to the first stage set of capacitors and the ramp circuit. The ramp circuit includes a feedback capacitor and a preset switch to provide a linear ramp output.
1. A multiple output constant slope ramp circuit, comprising:
a current source;
first and second transistors, operatively coupled to said current source; said first transistor providing a first output voltage comprising a first constant slope segment; said second transistor providing a second output voltage comprising a second constant slope segment, wherein the first constant slope segment differs from the second constant slope segment;
a capacitor operatively coupled to said first transistor and said current source; and
a first shorting switch operatively coupled between said first transistor and said second transistor.
2. The multiple output constant slope ramp circuit as claimed in claim 1 , further comprising:
a third transistor providing a third output voltage, and
a second shorting switch operatively coupled between said first transistor and said third transistor.
3. The multiple output constant slope ramp circuit as claimed in claim 1 , further comprising:
a voltage bias source; and
a switch operatively coupled between said voltage bias source and said capacitor.
4. The multiple output constant slope ramp circuit as claimed in claim 2 , further comprising: a voltage bias source; and
a switch operatively coupled between said voltage bias source and said capacitor.
5. The multiple output constant slope ramp circuit as claimed in claim 1 , further comprising:
a disconnect switch coupled between said first transistor and said capacitor to disconnect said capacitor during a sampling phase.