Granted Patent B2

US 7,944,767 · App. 12/488,086 · Granted May 17, 2011

Abstract

Claims (38)

1. A semiconductor device comprising a plurality of ports each of which includes a control terminal and a data terminal, wherein

in a first operation mode, each of the ports receives control information configured to execute data transmission/reception through its own data terminal, via its own control terminal, and

in a second operation mode, each of the ports receives the control information configured to execute data transmission/reception through its own data terminal, via its own control terminal and also at least one of the control terminals of the other ports.

2. The semiconductor device as claimed in claim 1 , wherein in the second operation mode, pieces of valid information are fetched from a data group relating to the control information that is received by using its own control terminal and also at least one of the control terminals of the other ports, and the pieces of valid information are combined to generate the control information.

3. The semiconductor device as claimed in claim 1 , wherein

each of the ports includes a memory cell array having a plurality of memory cells, and

the control information includes an address signal for selecting at least one of the memory cells.

4. The semiconductor device as claimed in claim 3 , wherein

each of the ports further includes a row address buffer and a column address buffer, and

the address signal includes a row address supplied to the row address buffer and a column address supplied to the column address buffer.

5. The semiconductor device as claimed in claim 4 , wherein the control information further includes a command signal for controlling the row address buffer and the column address buffer.

6. The semiconductor device as claimed in claim 1 , further comprising a mode controlling circuit bringing the plurality of ports into one of the first operation mode and the second operation mode.

7. The semiconductor device as claimed in claim 6 , wherein each of the ports includes a serial/parallel converter that serially receives the control information from its own control terminal.

8. The semiconductor device as claimed in claim 7 , wherein each of the serial/parallel converters converting serially inputted control information via its own control terminal into a parallel signal in the first operation mode.

9. The semiconductor device as claimed in claim 7 , wherein the serial/parallel converters generate a parallel signal based on the control information supplied in parallel to the control terminals.

10. A data processing system comprising:

a master device; and

a semiconductor device connected to the master device, wherein

the semiconductor device includes a plurality of circuit units each of which includes a serial port and executes a predetermined operation based on n-bit information inputted from outside,

at least one of the circuit units includes a first operation mode in which the n-bit information is inputted via its own serial port and a second operation mode in which the n-bit information is inputted via the own serial port and also a serial port of another circuit unit, and

the first operation mode and the second operation mode are switched according to mode designation information issued by the master device.

11. The data processing system as claimed in claim 10 , wherein

the semiconductor device is a semiconductor memory, and

the master device issues the mode designation information to designate the first operation mode or the second operation mode for each address region of the semiconductor memory.

12. A semiconductor device comprising:

a serial port; and

an input circuit that generates operation controlling information from information supplied to the serial port, wherein

the input circuit includes a first operation mode in which information appearing at the serial port in a first cycle is treated as valid information to generate the operation controlling information, and a second operation mode in which information appearing at the serial port in a second cycle different from the first cycle as valid information to generate the operation controlling information.

13. The semiconductor device as claimed in claim 12 , wherein

the input circuit is connected with a plurality of temporary memory circuits corresponding to number of bits inputted to the serial port,

the first cycle is a cycle in which the information is sequentially stored in the temporary memory circuits in synchronism with an internal clock, and in a subsequent internal clock in which the information is stored in all of the temporary memory circuits, all pieces of the information stored in the temporary memory circuits are fetched as the valid information, and

the second cycle is a cycle in which, in the subsequent internal clock in which the pieces of the information are stored in all of the temporary memory circuits, out of the pieces of the information stored in the temporary memory circuits, at least one piece of the information is fetched as the valid information.

14. A data processing system comprising:

a master device; and

a slave device that receives n-bit control information from the master device to perform data communication with the master device, wherein

the slave device includes m(m<n) serial ports each of which serially receives the control information, and

the master device divides the n-bit control information into each m bits, and also uses each of the m serial ports of the slave device to supply the n-bit control information to the slave device in n/m portions.

15. The data processing system as claimed in claim 14 , wherein the m serial ports of the slave device respectively fetches and shares at least one piece of valid information from an m-bit-unit data group each time the m-bit-unit data group is inputted, and internally generates the n-bit control information.

Assignments (6)