IP Library Granted Patent US 8,166,430
Granted Patent B2
US 8,166,430 · App. 12/488,672 · Granted Apr 24, 2012

Method for determining the quality of a quantity of properties, to be employed for verifying and specifying circuits

Assignee: Onespin Solutions GmbH
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Quick Facts
Patent No.
US 8,166,430
App. No.
12/488,672
Granted
Apr 24, 2012
Kind
B2
Abstract

A method is specified for determining the quality of a quantity of properties describing a machine, including a step for determining the existence of at least one sub-quantity of interrelated properties (P0, P1, . . . Pn) of the form Pi=(forall t. A i (t)=>Z i (t)), wherein A i (t) present an initial state and Z i (t) a target state for a corresponding property and at least one initial state A i is dependant on internal signals and including a step for checking whether at least one aspect of the input/output behavior of the machine described by the properties, which cannot be derived from an individual property P i , is described to such an accurate extent that one property Q exists, which represents this aspect without being dependant on the internal signals. The procedure is capable of providing a measurement and can particularly be used in the verification and specification of circuits.

Claims (16)

1. A computer-implemented method of functional verification of a digital circuit, wherein the digital circuit is checked with a set of properties representing a functioning of the digital circuit, wherein a quality factor of the set of properties has a predetermined value and wherein the properties determine a value series of internal values and output values for an input pattern, the input pattern comprising a temporal sequence of values of input values and an initial value of its internal values, the method comprising:

a) Determining an existence of at least one subset of interrelated properties (P 0 , P 1 , . . . P n );

b) Checking by a computer whether a value of a predetermined expression Q(t) is uniquely determined for at least one input pattern at at least one time point by means of an interaction of the least one subset of interrelated properties, whereby at said time point the value of the predetermined expression Q(t) is not uniquely determined by individual ones of the properties and wherein the predetermined expression is only dependent on values of the input values and the output values and the output values at time points; and

c) Outputting by a computer the quality factor based on said Q(t).

2. A computer-implemented generation method for a specification of a digital circuit having a set of properties representing a functioning of the digital circuit, wherein a quality factor of the set of properties has a predetermined value and wherein the properties determine a value series of internal values and output values for an input pattern, the input pattern comprising a temporal sequence of values of input values and an initial value of its internal values, the method comprising:

a) Determining an existence of at least one subset of interrelated properties (P 0 , P 1 , . . . P n );

b) Checking by a computer whether a value of a predetermined expression Q(t) is uniquely determined for at least one input pattern at least one time point by means of an interaction of the least one subset of interrelated properties, whereby at said time point the value of the predetermined expression Q(t) is not uniquely determined by individual ones of the properties and wherein the predetermined expression is only dependent on values of the input values and the output values and the output values at time points; and

c) Outputting by a computer the quality factor based on said Q(t).

3. A computer-implemented simulation-based verification method of a digital circuit utilizing monitors, wherein a quality of the monitors is determined using a quality factor of a set of properties representing a functioning of the monitors, and wherein the properties determine a value series of internal values and output values for an input pattern, the input pattern comprising a temporal sequence of values of input values and an initial value of its internal values, the method comprising:

a) Determining an existence of at least one subset of interrelated properties (P 0 , P 1 , . . . P n );

b) Checking by a computer whether a value of a predetermined expression Q(t) is uniquely determined for at least one input pattern at least one time point by means of an interaction of the least one subset of interrelated properties, whereby at said time point the value of the predetermined expression Q(t) is not uniquely determined by individual ones of the properties and wherein the predetermined expression is only dependent on values of the input values and the output values and the output values at time points; and

c) Outputting by a computer the quality factor based on said Q(t).

4. A computer-implemented simulation-based verification method of a digital circuit, wherein a coverage of the simulation-based verification is determined by set of monitors, wherein the set of monitors is defined based on a set of properties whose quality factor corresponds to a predetermined value and wherein the properties determine a value series of internal values and output values for an input pattern, the input pattern comprising a temporal sequence of values of input values and an initial value of its internal values, the method comprising:

a) Determining an existence of at least one subset of interrelated properties (P 0 , P 1 , . . . P n );

b) Checking by a computer whether a value of a predetermined expression Q(t) is uniquely determined for at least one input pattern at least one time point by means of an interaction of the least one subset of interrelated properties, whereby at said time point the value of the predetermined expression Q(t) is not uniquely determined by the individual properties and wherein the predetermined expression is only dependent on values of the input values and the output values and the output values at time points; and

c) Outputting by a computer the quality factor based on said Q(t).

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE CLERICAL ERROR OF ELCETRONIC TO ELECTRONIC PREVIOUSLY RECORDED ON REEL 063581 FRAME 0480. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME . Recorded May 16, 2023
From: ONESPIN SOLUTIONS GMBH
To: SIEMENS ELECTRONIC DESIGN AUTOMATION GMBH
Reel/Frame 063889/0548 →
MERGER AND CHANGE OF NAME Recorded May 9, 2023
From: ONESPIN SOLUTIONS GMBH; SIEMENS ELECTRONIC DESIGN AUTOMATION GMBH
To: SIEMENS ELCETRONIC DESIGN AUTOMATION GMBH
Reel/Frame 063581/0480 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2011
From: BUSCH, HOLGER
To: INFINEON TECHNOLOGIES AG
Reel/Frame 026074/0473 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2011
From: INFINEON TECHNOLOGIES AG
To: ONESPIN SOLUTIONS GMBH
Reel/Frame 026074/0533 →
EMPLOYMENT CONTRACT Recorded Apr 5, 2011
From: BORMANN, JORG
To: ONESPIN SOLUTIONS GMBH
Reel/Frame 026075/0560 →
Priority Claims (1)
EP 05020124 · Sep 15, 2005 · regional
Continuity (2)
Continuation 11459433 · Jul 24, 2006
Related Publication 20090327984A1 · Dec 31, 2009