Method and system for optimized power management for a network device supporting PCI-E and energy efficient ethernet
Aspects of a method and system for optimized power management for a network device supporting PCI-E and energy efficient Ethernet are provided. In this regard, in a network interface controller that supports energy efficient Ethernet, a PCI-E core may be transitioned from a low power PCI-E state to a full power PCI-E state when a PHY core in the network interface controller initiates transition from a low power mode to a full power mode and before the PHY core receives an Ethernet packet. In another embodiment, the PHY core in the network interface controller may be transitioned from a low power mode to a full power mode when the PCI-E core initiates transition from a low power PCI-E state to a full power PCI-E state, and before the PCI-E core receives a command to send an Ethernet packet.
1. A method for communication, comprising:
in a network interface controller that supports energy efficient Ethernet, performing using one or more circuits in said network interface controller:
transitioning a Peripheral Component Interconnect-Express (PCI-E) core from a low power PCI-E state to a full power PCI-E state in response to a PHY core in said network interface controller initiating a transition from a low power mode of the PHY core to a full power mode, where said PCI-E core transitions from said low power PCI-E state to said full power PCI-E state before said PHY core receives an Ethernet packet and where transitioning from said low power PCI-E state to said full power PCI-E state is started after a timer expires; and
configuring said timer for a third time period after said transition of said PHY core from said low power mode to said full power mode is started, if a first time period corresponding to said transition from said low power PCI-E state to said full power PCI-E state is less than a second time period corresponding to said transition of said PHY core from said low power mode to said full power mode or a speed of a network interface to said network interface controller is less than a threshold value.
2. The method according to claim 1 , wherein transitioning from said low power PCI-E state to said full power PCI-E state is started when said PHY core in said network interface controller starts transitioning from said low power mode to said full power mode, if said first time period corresponding to said transition from said low power PCI-E state to said full power PCI-E state is greater than said second time period corresponding to said transition of said PHY core from said low power mode to said full power mode or said speed of said network interface to said network interface controller is greater than or equal to the threshold value.
3. The method according to claim 1 , comprising configuring said timer for a fourth time period after receiving said Ethernet packet at said PHY core in said full power mode, if said first time period corresponding to said transition from said low power PCI-E state to said full power PCI-E state is less than said second time period corresponding to said transition of said PHY core from said low power mode to said full power mode and said first time period corresponding to said transition from said low power PCI-E state to said full power PCI-E state is less than a fifth time period corresponding to said receiving of said Ethernet packet at said PHY core in said full power mode.
4. The method of claim 1 , wherein said PHY core is configured to send or receive Ethernet packets via an Ethernet interface.
5. The method of claim 1 , wherein said network interface controller is communicatively coupled to a system chipset via said PCI-E core.
6. The method of claim 1 , wherein a medium access control (MAC) of said network interface controller includes said timer.
7. A method for communication, comprising:
in a network interface controller that supports energy efficient Ethernet, performing using one or more circuits in said network interface controller:
transitioning a PHY core in said network interface controller from a low power mode to a full Dower mode in response to a Peripheral Component Interconnect-Express (PCI-E) core initiating a transition from a low Dower PCI-E state to a full power PCI-E state, where said PHY core transitions from said low power mode to said full power mode before said PCI-E core receives a command to send an Ethernet packet and where transitioning from said low power mode of said PHY core to said full power mode is started when said PCI-E core transitions from said low power PCI-E state to said full power PCI-E state, if a first time period of said transition corresponding to said PCI-E core from said low power PCI-E state to said full power PCI-E state is less than a second time period corresponding to said transition from said low power mode of said PHY core to said full power mode.
8. The method of claim 7 , wherein said PHY core is configured to send or receive Ethernet packets via an Ethernet interface.
9. The method of claim 7 , wherein said network interface controller is communicatively coupled to a system chipset via said PCI-E core.
10. A method for communication, comprising:
in a network interface controller that supports energy efficient Ethernet, performing using one or more circuits in said network interface controller:
transitioning a PHY core in said network interface controller from a low power mode to a full power mode in response to a Peripheral Component Interconnect-Express (PCI-E) core initiating a transition from a low power PCI-E state to a full power PCI-E state, where said PHY core transitions from said low power mode to said full power mode before said PCI-E core receives a command to send an Ethernet packet and where transitioning from said low power mode to said full power mode is started based on one or both of: a first time period corresponding to said transition of said PCI-E core from said low power PCI-E state to said full power PCI-E state or a second time period corresponding to said transition of said PHY core from said low power mode to said full power mode and is started after a timer expires; and
configuring said timer for a third time period after said transition of said PCI-E core from said low power PCI-E state to said full power PCI-E state, if said first time period corresponding to said transition of said PCI-E core from said low power PCI-E state to said full power PCI-E state is less than said second time period corresponding to said transition from said low power mode to said full power mode.
11. The method of claim 10 , wherein said PHY core is configured to send or receive Ethernet packets via an Ethernet interface.
12. The method of claim 10 , wherein said network interface controller is communicatively coupled to a system chipset via said PCI-E core.
13. The method of claim 10 , wherein a medium access control (MAC) of said network interface controller includes said timer.
14. A system for communication, comprising:
one or more circuits in a network interface controller that supports energy efficient Ethernet, wherein said one or more circuits are operable to:
transition a Peripheral Component Interconnect-Express (PCI-E) core from a low power PCI-E state to a full power PCI-E state in response to a PHY core in said network interface controller initiating a transition from a low power mode of the PHY core to a full power mode, where said PCI-E core transitions from said low power PCI-E state to said full power PCI-E state before said PHY core receives an Ethernet packet and where said transition from said low power PCI-E state to said full power PCI-E state is started after a timer expires and is based on one or more of: a speed of a network interface to said network interface controller, a first time period corresponding to said transition from said low power PCI-E state to said full power PCI-E state, a second time period corresponding to said transition of said PHY core from said low power mode to said full power mode, or a speed of said PCI-E core to said network interface controller; and
configure said timer for a third time period after said transition of said PHY core from said low power mode to said full power mode is started, if said first time period corresponding to said transition from said low power PCI-E state to said full power PCI-E state is less than said second time period corresponding to said transition of said PHY core from said low power mode to said full power mode or said speed of said network interface to said network interface controller is less than a threshold value.
15. The system according to claim 14 , wherein said transition of said PCI-E core from said low power PCI-E state to said full power PCI-E state is started when said PHY core in said network interface controller starts transitioning from said low power mode to said full power mode, if said first time period corresponding to said transition from said low power PCI-E state to said full power PCI-E state is greater than said second time period corresponding to said transition of said PHY core from said low power mode to said full power mode or said speed of said network interface to said network interface controller is greater than or equal to the threshold value.
16. The system according to claim 14 , wherein said one or more circuits are operable to configure said timer for a fourth time period after receiving said Ethernet packet at said PHY core in said full power mode, if said first time period corresponding to said transition from said low power PCI-E state to said full power PCI-E state is less than said second time period corresponding to said transition of said PHY core from said low power mode to said full power mode and said first time period corresponding to said transition from said low power PCI-E state to said full power PCI-E state is less than a fifth time period corresponding to said receiving of said Ethernet packet at said PHY core in said full power mode.
17. The system of claim 14 , wherein said PHY core is configured to send or receive Ethernet packets via an Ethernet interface.
18. The system of claim 14 , wherein said network interface controller is communicatively coupled to a system chipset via said PCI-E core.
19. The system of claim 14 , wherein said network interface controller comprises a medium access control (MAC) including said timer.
20. A system for communication, comprising:
one or more circuits in a network interface controller that supports energy efficient Ethernet, wherein said one or more circuits are operable to:
transition a PHY core in said network interface controller from a low power mode to a full power mode in response to a Peripheral Component Interconnect-Express (PCI-E) core initiating a transition from a low power PCI-E state to a full power PCI-E state, where said PHY core transitions from said low power mode to said full power mode before said PCI-E core receives a command to send an Ethernet packet and where said transition of said PHY core from said low power mode to said full power mode is started when said PCI-E core transitions from said low power PCI-E state to said full power PCI-E state, if a first time period corresponding to said transition of said PCI-E core from said low power PCI-E state to said full power PCI-E state is less than a second time period corresponding to said transition from said low power mode of said PHY core to said full power mode.
21. The system of claim 20 , wherein said PHY core is configured to send or receive Ethernet packets via an Ethernet interface.
22. The system of claim 20 , wherein said network interface controller is communicatively coupled to a system chipset via said PCI-E core.
23. A system for communication, comprising:
one or more circuits in a network interface controller that supports energy efficient Ethernet, wherein said one or more circuits are operable to:
transition a PHY core in said network interface controller from a low power mode to a full power mode in response to a Peripheral Component Interconnect-Express (PCI-E) core initiating a transition from a low power PCI-E state to a full power PCI-E state, where said PHY core transitions from said low power mode to said full power mode before said PCI-E core receives a command to send an Ethernet packet and where said transition of said PHY core from said low power mode to said full power mode is started after a timer expires and is based on one or both of: a first time period corresponding to said transition of said PCI-E core from said low power PCI-E state to said full power PCI-E state or a second time period corresponding to said transition from said low power mode of said PHY core to said full power mode; and
configure said timer for a third time period after said transition of said PCI-E core from said low power PCI-E state to said full power PCI-E state, if said first time period corresponding to said transition of said PCI-E core from said low power PCI-E state to said full power PCI-E state is less than said second time period corresponding to said transition from said low power mode to said full power mode.
24. The system of claim 23 , wherein said PHY core is configured to send or receive Ethernet packets via an Ethernet interface.
25. The system of claim 23 , wherein said network interface controller is communicatively coupled to a system chipset via said PCI-E core.
26. The system of claim 23 , wherein said network interface controller comprises a medium access control (MAC) including said timer.