Internal voltage generating circuit of phase change random access memory device and method thereof

1. An internal voltage generating circuit, comprising:

a divided voltage generator configured to generate a divided voltage by dividing a feedback of an internal voltage at a division ratio that changes in response to an operation mode control signal;

a voltage detector configured to detect a level of the divided voltage based on a reference voltage level;

an internal voltage generator configured to receive a supply voltage as a power source and generate the internal voltage at a higher voltage level than the supply voltage in response to an output signal of the voltage detector; and

an under-driving unit configured to under-drive an internal voltage terminal to the supply voltage in an under-driving operation region that is determined in response to the operation mode control signal.

2. The internal voltage generating circuit of claim 1 , wherein the divided voltage generator includes:

a division control signal generator configured to receive the operation mode control signal swinging between the supply voltage and a ground voltage and output a division control signal swinging between the internal voltage and the ground voltage; and

a voltage divider configured to determine a level of the divided voltage by dividing a level of the internal voltage at a division ratio that changes in response to the division control signal.

3. The internal voltage generating circuit of claim 2 , wherein the voltage divider generates the divided voltage by dividing the internal voltage level by a factor of five when the division control signal has the internal voltage level, and

the voltage divider generates the divided voltage by dividing the internal voltage level by a factor of three when the division control signal has a ground voltage level.

4. The internal voltage generating circuit of claim 1 , wherein the voltage detector outputs a voltage detection signal having an activation state when the divided voltage level is lower than the reference voltage level, and

the voltage detector outputs the voltage detection signal having an inactivation state when the divided voltage level is higher than the reference voltage level.

5. The internal voltage generating circuit of claim 4 , wherein the internal voltage generator increases a level of the internal voltage by performing a positive charge pumping operation in response to the voltage detection signal having the activation state, and

the internal voltage generator does not increase a level of the internal voltage by holding off a positive charge pumping operation in response to the voltage detection signal of an inactivation state.

6. The internal voltage generating circuit of claim 1 , wherein the internal voltage generator includes:

an oscillation signal generator configured to generate an oscillation signal that toggles at a predetermined frequency in response to an output signal of the voltage detector; and

a charge pumping unit configured increase a level of an internal voltage terminal by performing a positive charge pumping operation in response to the oscillation signal.

7. The internal voltage generating circuit of claim 6 , wherein the oscillation signal generator toggles the oscillation signal at a predetermined frequency in response to activation of the output signal of the voltage detector, and

the oscillation signal generator sets up the oscillation signal to a predetermined logic level, with no toggling, in response to inactivation of the output signal of the voltage detector.

8. The internal voltage generating circuit of claim 7 , wherein the charge pumping unit increases a level of the internal voltage terminal by performing a positive charge pumping operation in response to toggling the oscillation signal at a predetermined frequency, and

the charge pumping unit does not increase a level of the internal voltage terminal by holding off a positive pumping operation in response to setting up the oscillation signal to a predetermined logic level without toggling.

9. The internal voltage generating circuit of claim 1 , wherein the under-driving unit includes:

an under-driving operation controller configured to generate an under-driving operation control signal in response to the operation mode control signal; and

an under-driver configured to under-drive a level of the internal voltage terminal to a supply voltage level in response to the under-driving operation control signal.

10. The internal voltage generating circuit of claim 9 , wherein the under-driving operation controller, in response to changing the operation mode control signal from an activation state to an inactivation state, inactivates the under-driving operation control signal after a predetermined time passes.

11. The internal voltage generating circuit of claim 10 , wherein the under-driver includes:

a level shifter configured to receive the under-driving operation control signal swinging between a supply voltage level and a ground voltage level and shift an upper limit level of the under-driving operation control signal to the internal voltage level; and

a short driver configured to drive the internal voltage terminal with a supply voltage by shorting the internal voltage terminal and a supply voltage terminal during an activation region of the under-driving operation control signal outputted from the level shifter.