PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICE
An operation for forming a trench after forming a via hole includes an operation for exposing a region for forming the via hole to light and an operation for exposing a region for forming the interconnect trench. More specifically, even if chemically amplified resist is buried in the via hole after the via hole is formed, then the region for forming of via hole is exposed to light again, so that the inside of the via hole is fully exposed to light. This allows removing the buried resist from the regions in via hole exposed to light, or namely the region and the region, with a developing solution, exposing at least a portion of the inner wall of the via hole to obtain the trench having a desired structure.
1 . A process for manufacturing a semiconductor device, including:
forming an etching-target film over a substrate;
forming a concave section over said etching-target film;
forming a chemically amplified resist film over said etching-target film;
exposing and developing said chemically amplified resist film to pattern thereof, forming an opening therein, at least a portion of an inner wall of said concave section being exposed through said opening; and
etching said etching-target film through a mask of said patterned chemically amplified resist film to form an interconnect trench,
wherein said exposing and developing said chemically amplified resist film includes exposing a region for forming said concave section to light, and also includes exposing a region for forming said interconnect trench to light.
2 . The process for manufacturing the semiconductor device as set forth in claim 1 , wherein two or more of said exposing the region for forming said concave section to light are conducted.
3 . The process for manufacturing the semiconductor device as set forth in claim 2 , wherein said exposing the region for forming said concave section to light is conducted after said exposing the region for forming said interconnect trench to light.
4 . The process for manufacturing the semiconductor device as set forth in claim 2 , wherein said exposing the region for forming said concave section to light is conducted before said exposing the region for forming said interconnect trench to light.