Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device comprising:

a memory cell string comprising memory cells connected in series;

a bit line electrically connected to one end of a current path of the memory cell string;

a source line electrically connected to the other end of the memory cell string;

a control circuit configured to perform a verify operation to check a write result after data is written to a memory cell of the memory cells connected in series; and

a voltage setting circuit connected to the bit line through a transistor, the voltage setting circuit being configured to set a charging voltage for the bit line in a verify operation and a read operation and to make a first charging voltage in a read operation higher than a second charging voltage in a verify operation, the first and second charging voltages being higher than a ground voltage,

wherein the control circuit determines whether the bit line has been discharged by the memory cell after the bit line has been charged to the first and second charging voltages in a read operation and verify operation, respectively.

2. The device according to claim 1 , wherein

the memory cell stores n bits (n is a natural number not less than 2),

the control circuit carries out a write operation and a verify operation in each of m stages (m≦n), the number of stages becoming larger as the number of bits stored in the memory cell increases, and

the voltage setting circuit makes the charging voltage higher in a later stage.

3. The device according to claim 1 , further comprising word lines connected to gates of the memory cells,

wherein the control circuit applies a verify voltage and a read voltage to the word lines in a verify operation and a read operation.

4. The device according to claim 1 , further comprising a sense amplifier configured to detect the data written to the memory cell.

5. The device according to claim 1 , wherein the voltage setting circuit includes a clamp transistor which has a source electrically connected to the bit line and a drain electrically connected to a power supply and a regulator which controls a gate voltage of the clamp transistor.

6. The device according to claim 1 , wherein the memory cell includes a first insulating film, a charge storage layer, a second insulating film, and a gate electrode which are sequentially stacked on a semiconductor substrate.

7. The device according to claim 1 , wherein

when setting the memory cell to a first threshold voltage, the control circuit is configured to perform a first verify operation using a second threshold voltage lower than the first threshold voltage and a second verify operation using the first threshold voltage; and

the voltage setting circuit is configured to make a charging voltage in the second verify operation higher than a charging voltage in the first verify operation.

8. The device according to claim 1 , wherein a charging voltage is constant in one verify operation.

9. A nonvolatile semiconductor memory device comprising:

a memory cell string comprising memory cells connected in series, each of the memory cells storing n bits (n is a natural number not less than 2);

a bit line electrically connected to one end of the memory cell string;

a source line electrically connected to the other end of the memory cell string;

a control circuit configured to perform a verify operation to check a write result after data is written to the memory cell, the control circuit being configured to carry out a write operation and a verify operation in each of m stages (m≦n), the number of stages becoming larger as the number of bits stored in the memory cell increases; and

a voltage setting circuit connected to the bit line through a transistor, the voltage setting circuit being configured to set a charging voltage for the bit line in a verify operation and to make the charging voltage higher in a later stage, the charging voltages being higher than a ground voltage,

wherein the control circuit determines whether the bit line has been discharged by the memory cell after the bit line has been charged to the charging voltage.

10. The device according to claim 9 , further comprising word lines connected to gates of the memory cells,

wherein the control circuit is configured to apply a verify voltage and a read voltage to the word lines in a verify operation and a read operation.

11. The device according to claim 9 , further comprising a sense amplifier configured to detect the data written to the memory cell.

12. The device according to claim 9 , wherein the voltage setting circuit includes a clamp transistor which has a source electrically connected to the bit line and a drain electrically connected to a power supply and a regulator configured to control a gate voltage of the clamp transistor.

13. The device according to claim 9 , wherein the memory cell includes a first insulating film, a charge storage layer, a second insulating film, and a gate electrode which are sequentially stacked on a semiconductor substrate.

14. The device according to claim 9 , wherein

when setting the memory cell to a first threshold voltage, the control circuit is configured to perform a first verify operation using a second threshold voltage lower than the first threshold voltage and a second verify operation using the first threshold voltage; and

the voltage setting circuit is configured to make a charging voltage in the second verify operation higher than a charging voltage in the first verify operation.

15. The device according to claim 9 , wherein a charging voltage is constant in one verify operation.

16. The device according to claim 1 , wherein the voltage setting circuit includes a clamp transistor which has a source electrically connected to the bit line and a drain electrically connected to a power supply via at least one transistor and a regulator which controls a gate voltage of the clamp transistor.