SOLID STATE DEVICE WITH ALLOCATED FLASH CACHE

1 . A method of transferring data in a flash storage device comprising a random access memory and a flash memory, the method comprising:

receiving data from a host system, the data comprising a data segment;

temporarily storing the data segment in a data buffer of the random access memory;

assigning the data segment to a logical block address;

determining if the data segment stored in the data buffer comprises sequential data or random data; and

writing the data segment to an allocated cache portion of the flash memory if the data segment is determined to comprise random data.

2 . The method of claim 1 , further comprising a second writing step of writing the data segment from the allocated cache portion of the flash memory to a main storage portion of the flash memory.

3 . The method of claim 1 , wherein the flash memory comprises an array of plurality of flash memory units, and the allocated cache portion of the flash memory is evenly distributed across the plurality of flash memory units.

4 . The method of claim 1 , wherein the flash memory comprises an array of plurality of flash memory units, and the allocated cache portion of the flash memory is not uniformly distributed across the plurality of flash memory units.

5 . (canceled)

6 . The method of claim 2 , wherein in the second writing step the data segment is written from the allocated cache portion to a location in the main storage portion that corresponds to the logical block address assigned to the data segment.

7 . The method of claim 6 , wherein in the second writing step a plurality of other data segments having the same assigned logical block address as the data segment are written along with the data segment to the location in the main storage portion that corresponds to the assigned logical block address.

8 . The method of claim 7 , wherein the second writing step is not conducted until a predetermined number of data segments having the same assigned logical block address have been written to the allocated cache portion of the flash memory.

9 . The method of claim 8 , wherein the allocated cache portion of the flash memory and the main storage portion of the flash memory are each comprised of a plurality of flash data blocks each of which is sized to accommodate the predetermined number of data segments.

10 . The method of claim 1 , wherein the allocated cache portion of the flash memory and the main storage portion of the flash memory are each comprised of a plurality of flash data blocks.

11 . The method of claim 7 , wherein the data segment and the plurality of other data segments are sequential data segments.

12 . The method of claim 2 , further comprising:

maintaining an address table in the random access memory, wherein the address table comprises a plurality of logical block addresses cross-referenced to a plurality of physical addresses; and

updating the address table upon writing the data segment from the allocated cache portion to a location in the main storage portion of the flash memory by storing the physical address of the location as a cross-reference to the logical block address assigned to the data segment.

13 . The method of claim 12 , wherein the address table also includes a cross-reference between the plurality of logical block addresses and a plurality of allocated cache portion indicators, each indicator indicating that a data segment corresponding to the respective logical block address is stored in the allocated cache portion of the flash memory.

14 . The method of claim 13 , wherein the each of the plurality of allocated cache portion indicators is a physical address pointing to a different logical block cache table stored in the random access memory, the logical block cache table comprising a list of all data segments stored in the allocated cache portion that correspond to the same logical block address which is cross-referenced to the allocated cache portion indicator.

15 . The method of claim 14 , wherein the logical block cache table is a link list of all data segments stored in the allocated cache portion that correspond to the same logical block address which is cross-referenced to the allocated cache portion indicator.

16 . The method of claim 14 , wherein the logical block cache table also includes a physical address of a location in the allocated cache portion where each data segment listed in the logical block cache table is stored.

17 . The method of claim 1 , further comprising:

writing the data segment from the data buffer of the random access memory to a main storage portion of the flash memory without temporarily storing the data segment in the allocated cache portion of the flash memory if the data segment is determined to comprise sequential data.

18 . The method of claim 17 , wherein a plurality of other data segments having the same assigned logical block address as the data segment are written along with the data segment to a location in the main storage portion of the flash memory that corresponds to the assigned logical block address.

19 . The method of claim 12 , further comprising:

storing a copy of the address table in the flash memory prior to a power-down operation of the flash storage device; and

transferring the address table from the flash memory to the random access memory upon power-up operation of the flash storage device.

20 . The method of claim 19 , wherein in the storing step, a normal power- down indicator tag is also stored in flash memory, and further comprising a reconstruction step, which upon power-up operation of the flash storage device checks the flash memory for the presence of a normal power-down indicator tag, wherein, in the case that the normal power-down indicator tag is not present, all data segments in flash memory are scanned to gather information related to all data segments present in flash memory and their corresponding logical block addresses, and the address table is reconstructed based on the gathered information.

21 . The method of claim 2 , further comprising:

conducting a background cleanup operation in which the allocated cache portion is scanned to identify a set of data segments that collectively contain a set of sequential data, and writing the set of data segments to the main storage portion of the flash memory, upon which each one of the set of data segments is identified as in invalid data segment.

22 . The method of claim 21 , wherein the flash memory is comprised of a plurality of flash data blocks, and wherein the background cleanup operation further includes selecting a flash data block which has a predetermined number of invalid data segments and then erasing the selected flash data block for subsequent use and identifying the selected flash data block as an erased flash data bock.

23 . The method of claim 22 , wherein in the background cleanup operation all data segments in the selected flash data block which are not identified as an invalid data segment are moved to another flash data block in the allocated cache portion before the selected flash data block is erased.

24 . The method of claim 22 , wherein the background cleanup operation continues until a predetermined percentage of all flash data blocks are identified as erased flash data bocks.

25 . A flash storage device comprising:

a flash memory;

a random access memory; and

a controller configured to perform the steps of:

receiving data from a host system, the data comprising a data segment;

temporarily storing the data segment in a data buffer of the random access memory;

assigning the data segment to a logical block address;

determining if the data segment stored in the data buffer comprises sequential data or random data; and

writing the data segment to an allocated cache portion of the flash memory if the data segment is determined to comprise random data.

26 . The flash storage device of claim 25 , the controller being further configured to perform a second writing step of writing the data segment from the allocated cache portion of the flash memory to a main storage portion of the flash memory.

27 . The flash storage device of claim 25 , wherein the flash memory comprises an array of plurality of flash memory units, and the allocated cache portion of the flash memory is evenly distributed across the plurality of flash memory units.

28 . The flash storage device of claim 25 , wherein the flash memory comprises an array of plurality of flash memory units, and the allocated cache portion of the flash memory is not uniformly distributed across the plurality of flash memory units.

29 . (canceled)

30 . The flash storage device of claim 26 , wherein in the second writing step the data segment is written from the allocated cache portion to a location in the main storage portion that corresponds to the logical block address assigned to the data segment.

31 . The flash storage device of claim 30 , wherein in the second writing step a plurality of other data segments having the same assigned logical block address as the data segment are written along with the data segment to the location in the main storage portion that corresponds to the assigned logical block address.

32 . The flash storage device of claim 31 , wherein the second writing step is not conducted until a predetermined number of data segments having the same assigned logical block address have been written to the allocated cache portion of the flash memory.

33 . The flash storage device of claim 32 , wherein the allocated cache portion of the flash memory and the main storage portion of the flash memory are each comprised of a plurality of flash data blocks each of which is sized to accommodate the predetermined number of data segments.

34 . The flash storage device of claim 25 , wherein the allocated cache portion of the flash memory and the main storage portion of the flash memory are each comprised of a plurality of flash data blocks.

35 . The flash storage device of claim 31 , wherein the data segment and the plurality of other data segments are sequential data segments.

36 . The flash storage device of claim 26 , the controller being further configured to perform the steps of :

maintaining an address table in the random access memory, wherein the address table comprises a plurality of logical block addresses cross-referenced to a plurality of physical addresses; and

updating the address table upon writing the data segment from the allocated cache portion to a location in the main storage portion of the flash memory by storing the physical address of the location as a cross-reference to the logical block address assigned to the data segment.

37 . The flash storage device of claim 36 , wherein the address table also includes a cross-reference between the plurality of logical block addresses and a plurality of allocated cache portion indicators, each indicator indicating that a data segment corresponding to the respective logical block address is stored in the allocated cache portion of the flash memory.

38 . The flash storage device of claim 37 , wherein the each of the plurality of allocated cache portion indicators is a physical address pointing to a different logical block cache table stored in the random access memory, the logical block cache table comprising a list of all data segments stored in the allocated cache portion that correspond to the same logical block address which is cross-referenced to the allocated cache portion indicator.

39 . The flash storage device of claim 38 , wherein the logical block cache table is a link list of all data segments stored in the allocated cache portion that correspond to the same logical block address which is cross-referenced to the allocated cache portion indicator.

40 . The flash storage device of claim 38 , wherein the logical block cache table also includes a physical address of a location in the allocated cache portion where each data segment listed in the logical block cache table is stored.

41 . The flash storage device of claim 26 , the controller being further configured to perform the step of:

writing the data segment from the data buffer of the random access memory to a main storage portion of the flash memory without temporarily storing the data segment in the allocated cache portion of the flash memory if the data segment is determined to comprise sequential data.

42 . The flash storage device of claim 41 , wherein a plurality of other data segments having the same assigned logical block address as the data segment are written along with the data segment to a location in the main storage portion of the flash memory that corresponds to the assigned logical block address.

43 . The flash storage device of claim 36 , the controller being further configured to perform the steps of:

storing a copy of the address table in the flash memory prior to a power-down operation of the flash storage device; and

transferring the address table from the flash memory to the random access memory upon power-up operation of the flash storage device.

44 . The flash storage device of claim 43 , wherein in the storing step, a normal power-down indicator tag is also stored in flash memory, and the controller being further configured to perform a reconstruction step, which upon power-up operation of the flash storage device checks the flash memory for the presence of a normal power-down indicator tag, wherein, in the case that the normal power-down indicator tag is not present, all data segments in flash memory are scanned to gather information related to all data segments present in flash memory and their corresponding logical block addresses, and the address table is reconstructed based on the gathered information.

45 . The flash storage device of claim 26 , the controller being further configured to perform the step of:

conducting a background cleanup operation in which the allocated cache portion is scanned to identify a set of data segments that collectively contain a set of sequential data, and writing the set of data segments to the main storage portion of the flash memory, upon which each one of the set of data segments is identified as in invalid data segment.

46 . The flash storage device of claim 45 , wherein the flash memory is comprised of a plurality of flash data blocks, and wherein the background cleanup operation further includes selecting a flash data block which has a predetermined number of invalid data segments and then erasing the selected flash data block for subsequent use and identifying the selected flash data block as an erased flash data bock.

47 . The flash storage device of claim 46 , wherein in the background cleanup operation all data segments in the selected flash data block which are not identified as an invalid data segment are moved to another flash data block in the allocated cache portion before the selected flash data block is erased.

48 . The flash storage device of claim 46 , wherein the background cleanup operation continues until a predetermined percentage of all flash data blocks are identified as erased flash data bocks.

49 . A non-transitory machine readable medium carrying one or more sequences of instructions for managing memory operations in a flash storage device having a flash memory, a random access memory and a controller, wherein execution of the one or more sequences of instructions by one or more processors in the controller cause the one or more processors to perform the steps of:

receiving data from a host system, the data comprising a data segment;

temporarily storing the data segment in a data buffer of the random access memory;

assigning the data segment to a logical block address;

determining if the data segment stored in the data buffer comprises sequential data or random data; and

writing the data segment to an allocated cache portion of the flash memory if the data segment is determined to comprise random data.