Non-volatile semiconductor memory device and method of writing data in non-volatile semiconductor memory devices

1. A non-volatile semiconductor memory device, comprising:

a NAND cell unit including a plurality of electrically rewritable non-volatile memory cells serially connected, the NAND cell unit having one end connected to a bit line via a first selection gate transistor and an other end connected to a source line via a second selection gate transistor;

a first dummy cell interposed next to the first selection gate transistor in the NAND cell unit; and

a second dummy cell interposed next to the second selection gate transistor in the NAND cell unit,

wherein the device has a data write mode to boost a first boost channel region that contains a non-write selected memory cell and non-selected memory cells located closer to the first selection gate transistor than the selected memory cell, and a second boost channel region that contains non-selected memory cells located closer to the second selection gate transistor than the selected memory cell, both the first and second boost channel being electrically separated from each other in the NAND cell unit,

wherein in the data write mode, a first non-selection voltage applied to the first dummy cell is kept constant irrespective of a position of the selected memory cell in the NAND cell unit.

2. The non-volatile semiconductor memory device according to claim 1 , wherein in the data write mode, a non-selection voltage applied to the second dummy cell is switched at least between a first voltage V 1 and a second voltage V 2 (>V 1 ) in accordance with the position of the selected memory cell in the NAND cell unit.

3. The non-volatile semiconductor memory device according to claim 2 , wherein the first non-selection voltage is higher than the first voltage V 1 .

4. The non-volatile semiconductor memory device according to claim 1 ,

wherein in the data write mode a write voltage Vpgm is applied to the selected memory cell, a write non-selection voltage Vm (<Vpgm) to a first non-selected memory cell contained in the first boost channel region, a channel separation voltage Vb (<Vm) to a second non-selected memory cell or a non-selected memory cell located closer to the second selection gate transistor than the selected memory cell, and a voltage Va (Vb<Va<Vm) to a third non-selected memory cell located between the second non-selected memory cell and the selected memory cell,

wherein in the data write mode a write non-selection voltage applied to the second dummy cell is switched to a first voltage V 1 (Vb<V 1 <Vm) when the selected memory cell locates in a first cell region set closer to the first selection gate transistor in the NAND cell unit, and to a second voltage V 2 (Vb<V 1 <V 2 ≦Vm) when the selected memory cell locates in a second cell region set closer to the second selection gate transistor than the first cell region.

5. The non-volatile semiconductor memory device according to claim 4 , wherein non-selected memory cells located closer to the second selection gate transistor than the selected memory cell include non-selected memory cells, except the second non-selected memory cell and the third non-selected memory cell, the non-selected memory cells being supplied with the write non-selection voltage Vm.

6. The non-volatile semiconductor memory device according to claim 1 , wherein the first non-selection voltage is lower than a voltage applied to the non-selected memory cells.