Control method for nonvolatile memory and semiconductor device

1. A control method for a nonvolatile memory in a system including:

a nonvolatile memory;

a random number generator operable to generate a random number; and

a controller coupled to the random number generator and operable to access the nonvolatile memory,

the control method for the nonvolatile memory comprising the step of:

making the controller perform refresh control to determine a refresh-targeted area based on a random number generated by the random number generator every time access to the nonvolatile memory is performed, and to re-write to the refresh-targeted area concerned.

2. A control method for a nonvolatile memory in a system including:

a nonvolatile memory; and

a controller operable to access the nonvolatile memory,

the control method for the nonvolatile memory comprising the step of:

making the controller perform refresh control to manage a total number of access to all accessing target areas and a refresh-targeted area in the nonvolatile memory, to update the total number of access to the nonvolatile memory every time access to the nonvolatile memory is performed, and to re-write to the refresh-targeted area based on the result of the updating.

3. The control method for the nonvolatile memory according to claim 2 ,

wherein the refresh control performed by the controller includes:

first processing for obtaining a total number of access to all accessing target areas in the nonvolatile memory, every time access to the nonvolatile memory is performed;

second processing for comparing the total number obtained in the first processing with a prescribed threshold;

third processing for performing re-writing to the refresh-targeted area according to the comparison result in the second processing; and

fourth processing for updating the threshold according to need after the third processing.

4. The control method for the nonvolatile memory according to claim 2 ,

wherein the refresh control performed by the controller includes:

fifth processing for obtaining difference between the total number of access to all accessing target areas in the nonvolatile memory and the number of access to every accessing target area in the nonvolatile memory, every time access to the nonvolatile memory is performed;

fifth processing for comparing the difference obtained in the fifth processing with a prescribed threshold; and

seventh processing for determining a refresh-targeted area depending on the difference obtained in the sixth processing and for performing re-writing in order to refresh the refresh-targeted area.

5. The control method for the nonvolatile memory according to claim 2 ,

wherein the refresh control performed by the controller includes:

eighth processing for obtaining difference between the total number of access to all accessing target areas in the nonvolatile memory and the number of access to every accessing target area in the nonvolatile memory, every time access to the nonvolatile memory is performed;

ninth processing for obtaining a first accessing target area corresponding to the difference smaller than a prescribed threshold, among the difference obtained in the eighth processing;

tenth processing for determining whether interchange of a physical address to a logical address is possible between the first accessing target area obtained in the ninth processing and a second accessing target area different from the first accessing target area;

eleventh processing for performing the interchange of the physical address to the logical address between the first accessing target area and the second accessing target area, when it is determined in the tenth processing that the interchange of the physical address to the logical address between the first accessing target area and the second accessing target area is possible; and

twelfth processing for determining a refresh-targeted area according to the difference obtained in the eighth processing and for performing re-writing to refresh the refresh-targeted area, when it is determined in the tenth processing that the interchange of the physical address to the logical address is impossible.

6. The control method for the nonvolatile memory according to claim 5 ,

wherein the second accessing target area is determined based on the difference obtained in the eighth processing.

7. A semiconductor device including a nonvolatile memory, the semiconductor device comprising:

a random number generator operable to generate a random number; and

a controller operable to determine a refresh-targeted area based on a random number generated by the random number generator and operable to perform refresh control in order to perform re-writing to the refresh-targeted area concerned, every time access to the nonvolatile memory is performed.

8. A semiconductor device including a nonvolatile memory, the semiconductor device comprising:

a management area operable to manage a total number of access to all accessing target areas and a refresh-targeted area in the nonvolatile memory; and

a controller operable to update the total number of access to the nonvolatile memory and to perform refresh control in order to perform re-writing to the refresh-targeted area based on the updated result, every time access to the nonvolatile memory is performed.

9. The semiconductor device according to claim 8 ,

wherein the management area is formed by a part of a storage area in the nonvolatile memory.

10. The semiconductor device according to claim 8 ,

wherein the management area is formed by a semiconductor memory provided separately from the nonvolatile memory.

11. The semiconductor device according to claim 8 ,

wherein the controller performs processing including:

first processing for obtaining a total number of access to all accessing target areas in the nonvolatile memory, every time access to the nonvolatile memory is performed;

second processing for comparing the total number of access obtained in the first processing with a prescribed threshold;

third processing for performing re-writing to the refresh-targeted area according to the comparison result in the second processing; and

fourth processing for updating the threshold according to need after the third processing.

12. The semiconductor device according to claim 8 ,

wherein the controller performs processing including:

fifth processing for obtaining difference between the total number of access to all accessing target areas in the nonvolatile memory and the number of access to every accessing target area in the nonvolatile memory, every time access to the nonvolatile memory is performed;

fifth processing for comparing the difference obtained in the fifth processing with a prescribed threshold; and

seventh processing for determining a refresh-targeted area depending on the difference obtained in the sixth processing and for performing re-writing in order to refresh the refresh-targeted area.

13. The semiconductor device according to claim 8 further comprising:

a logical address/physical address conversion table operable to convert a logical address given externally to a physical address in the nonvolatile memory,

wherein the controller performs processing including:

eighth processing for obtaining difference between the total number of access to all accessing target areas in the nonvolatile memory and the number of access to every accessing target area in the nonvolatile memory, every time access to the nonvolatile memory is performed;

ninth processing for obtaining a first accessing target area corresponding to the difference smaller than a prescribed threshold, among the difference obtained in the eighth processing;

tenth processing for determining whether interchange of a physical address to a logical address is possible between the first accessing target area obtained in the ninth processing and a second accessing target area different from the first accessing target area;

eleventh processing for performing the interchange of the physical address to the logical address between the first accessing target area and the second accessing target area, when it is determined in the tenth processing that the interchange of the physical address to the logical address between the first accessing target area and the second accessing target area is possible; and

twelfth processing for determining a refresh-targeted area according to the difference obtained in the eighth processing and for performing re-writing to refresh the refresh-targeted area, when it is determined in the tenth processing that the interchange of the physical address to the logical address is impossible.