IP Library Granted Patent US 8,169,009
Granted Patent B2
US 8,169,009 · App. 12/494,885 · Granted May 1, 2012

Semiconductor device

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Quick Facts
Patent No.
US 8,169,009
App. No.
12/494,885
Granted
May 1, 2012
Kind
B2
Abstract

A semiconductor device includes N fins made of semiconductor regions aligned in parallel with each other in the top view plain, a gate electrode formed on both side surfaces of each of the N fins to cross the fins, source/drain layers formed in each of the N fins by sandwiching the gate electrode, a first wiring connected to one of the source/drain layers via a first contact formed in each of M fins, and a second wiring connected to the other one of the source/drain layers via a second contact formed in each of K fins.

Claims (11)

1. A semiconductor device comprising:

N (N is an integer equal to or larger than 2) fins made of a semiconductor material aligned in parallel with each other;

a gate electrode formed on both side surfaces of the N fins to cross the fins;

source/drain layers formed in each of the N fins by sandwiching the gate electrode;

a first wiring connected to one of the source/drain layers via a first contact formed in M fins (M is an integer equal to or larger than 2 and equal to or smaller than N); and

a second wiring connected to the other one of the source/drain layers via a second contact formed in K fins (K is an integer smaller than M) and isolated from the first wiring, wherein the first and second contacts are associated with the same gate electrode.

2. The semiconductor device according to claim 1 , further comprising at least one dummy fin aligned in parallel at outside of the N fins.

3. The semiconductor device according to claim 1 , wherein widths of the fins are equal to each other, and intervals between the fins are also equal to each other.

4. The semiconductor device according to claim 1 , wherein the first contact is aligned in the M fins to be symmetrical with each other in the top view plain, and the second contact is aligned in the K fins to be symmetrical with each other in the top view plain.

5. The semiconductor device according to claim 1 , wherein the fins are not doped with impurity.

6. The semiconductor device according to claim 1 , wherein the gate electrode is configured by metal compounds.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 11, 2017
From: TOSHIBA CORPORATION
To: MICROSOFT TECHNOLOGY LICENSING, LLC
Reel/Frame 041333/0955 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2009
From: INABA, SATOSHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 022899/0922 →