Timing over packet performance
The invention is directed to a method and apparatus for providing improved packet over timing clock synchronization in a packet switching network using Operations, Administration, and Maintenance (OAM) tools to compensate for asymmetrical characteristics between forward and reverse data paths.
1. A method of providing clock synchronization in a packet switching network between a first network element having a first clock and a second network element having a second clock, the method comprising:
receiving, at the second network element, asymmetry characteristics between a forward path and a reverse path, the forward path from the first network element to the second network element, and the reverse path from the second network element to the first network element, wherein the asymmetric characteristics comprise average residence time per node in the forward path and the reverse path;
calculating, at the second network element, an asymmetry factor;
receiving, at the second network element at a first receive time, a synchronization packet containing a first transmit time from the first network element;
transmitting, from the second network element to the first network element at a second transmit time, a delay request packet;
receiving, at the second network element, a delay response packet containing a second receive time, from the first network element;
calculating, at the second network element, a clock offset using the asymmetry factor, the first and second transmit times, and the first and second receive times; and
synchronizing, at the second network element, the second clock with the first clock using the clock offset.
2. The method of claim 1 , wherein the asymmetry characteristics further comprise link speed and link distance parameters.
3. The method of claim 2 , wherein the network topology information further comprises:
a number of first network elements on the forward path and a number of second network elements on the reverse path; and
a type of each of the first and the second network elements.
4. The method of claim 2 , wherein the network topology information is derived from a manually pre-populated table.
5. The method of claim 1 , wherein the step of receiving the asymmetry characteristics further comprises:
receiving end-to-end throughput statistics.
6. The method of claim 1 , wherein the asymmetry characteristics further comprise link loading information.
7. The method of claim 6 , wherein the asymmetry characteristics further comprise a transmission delay weight for a link with a particular load percentage.
8. The method of claim 1 , wherein the asymmetry characteristics further comprise an expected intra-node switching delay for a particular node type.
9. An apparatus for providing clock synchronization from a first network element having a first clock in a packet switching network, the apparatus comprising:
a first interface for receiving synchronization packets from the first network element;
a second interface for transmitting delay request packets to the first network element;
an asymmetry estimator configured to receive asymmetry characteristics, between a forward path and a reverse path, the forward path being from the first network element to a second network element, and the reverse path from the second network element to the first network element, wherein the asymmetry estimator is further configured to calculate an asymmetry factor from the asymmetry characteristics and the asymmetric characteristics comprise average residence time per node in the forward path and the reverse path.
10. The apparatus of claim 9 , further comprising:
a second clock, wherein the second clock is configured to
receive, at the first interface at a first receive time, a synchronization packet containing a first transmit time from the first network element,
transmit, from the second interface to the first network element at a second transmit time, a delay request packet,
receive, at the first interface, a delay response packet containing a second receive time, from the first network element; and
calculate a clock offset using the asymmetry factor, the first and second transmit times, and the first and second receive times.
11. The apparatus of claim 10 , wherein
the second clock is configured to synchronize to the first clock on the first network element using the clock offset.
12. The apparatus of claim 11 , wherein the apparatus is further configured to
receive, at the first interface at a first receive time, a synchronization packet containing a first transmit time from the second network element,
transmit from the second interface, to the second network element at a second transmit time, a delay request packet,
receive at the second interface, a delay response packet containing a second receive time, from the second network element,
calculate at the second network element, a clock offset using the asymmetry factor, and
synchronize at the second network element, the second clock with the first clock using the clock offset, the first and second transmit times, and the first and second receive times.
13. The apparatus of claim 9 , wherein the asymmetry characteristics further comprise link speed and link distance parameters.
14. The apparatus of claim 13 , wherein the network topology information comprises the number of network elements on the forward path and the number of network elements on the reverse path, and the type of each of the first and second network elements.
15. The apparatus of claim 14 , wherein the asymmetry estimator is configured to receive the network topology information from a manually pre-populated table.
16. The apparatus of claim 9 , wherein the asymmetry characteristics comprise end-to-end throughput statistics.
17. The apparatus of claim 9 , wherein the asymmetry characteristics further comprise link loading information.
18. The apparatus of claim 17 , wherein the asymmetry characteristics further comprise a transmission delay weight for a link with a particular load percentage.
19. The apparatus of claim 9 , wherein the asymmetry characteristics further comprise an expected intra-node switching delay for a particular node type.
20. A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform the method of claim 1 .