System, method, and computer program product for optimizing an altered hardware design utilizing power reports
View Patent ↗A system, method and computer program product are provided for optimizing an altered hardware design utilizing power reports. In use, a first hardware design is synthesized. Additionally, a first power report is generated for the synthesized first hardware design. Further, the first hardware design is altered. Further still, the altered hardware design is synthesized. Also, a second power report is generated for the synthesized altered hardware design. Furthermore, the altered hardware design is optimized utilizing the first power report and the second power report.
1. A computer program product embodied on a non-transitory computer readable medium, comprising:
computer code for synthesizing a first hardware design;
computer code for generating a first power report for the synthesized first hardware design;
computer code for altering the first hardware design;
computer code for synthesizing the altered hardware design;
computer code for generating a second power report for the synthesized altered hardware design; and
computer code for optimizing the altered hardware design, utilizing the first power report and the second power report;
wherein the computer program product is operable such that the first power report and the second power report are compared for determining one or more registers that have increased in power usage from the first hardware design to the altered hardware design;
wherein the optimizing includes identifying one or more registers to be retimed in the altered hardware design;
wherein the computer program product is operable such that the first power report and the second power report are used to identity the one or more registers to be retimed.
2. The computer program product of claim 1 , further comprising computer code for synthesizing the optimized hardware design.
3. The computer program product of claim 1 , further comprising computer code for re-mapping the optimized hardware design.
4. The computer program product of claim 1 , further comprising computer code for identifying all altered registers in the synthesized altered hardware design.
5. The computer program product of claim 1 , wherein the computer program product is operable such that the first power report indicates the power usage of all registers in the synthesized first hardware design.
6. The computer program product of claim 1 , further comprising computer code for generating clock gating efficiency reports for all registers in the altered hardware design.
7. The computer program product of claim 1 , wherein the optimizing includes dissolving one or more hierarchies in the altered hardware design.
8. The computer program product of claim 1 , wherein the optimizing includes creating one or more new hierarchies in the altered hardware design.
9. The computer program product of claim 1 , wherein the altering includes performing sequential clock gating on the first hardware design.
10. The computer program product of claim 1 , wherein the altering includes changing a timing constraint of the first hardware design.
11. The computer program product of claim 1 , wherein the optimizing includes creating retimed hierarchies in the altered hardware design.
12. The computer program product of claim 1 , further comprising computer code for verifying the optimized hardware design.
13. The computer program product of claim 1 , wherein synthesizing the first hardware design includes performing combinational clock gating on the first hardware design.
14. The computer program product of claim 1 , further comprising computer code for simulating a synthesized gate level netlist of the synthesized first hardware design for obtaining gate level simulation vectors.
15. The computer program product of claim 1 , wherein optimizing the altered hardware design includes performing one or more timing alterations to one or more components of the altered hardware design;
wherein the optimizing includes identifying one or more registers to be retimed in the altered hardware design;
wherein the system is operable such that the first power report and the second power report are used to identity the one or more registers to be retimed.
16. A computer-implemented method, comprising:
synthesizing a first hardware design, utilizing a processor;
generating a first power report for the synthesized first hardware design;
altering the first hardware design;
synthesizing the altered hardware design;
generating a second power report for the synthesized altered hardware design; and
optimizing the altered hardware design, utilizing the first power report and the second power report;
wherein the first power report and the second power report are compared for determining one or more registers that have increased in power usage from the first hardware design to the altered hardware design;
wherein the optimizing includes identifying one or more registers to be retimed in the altered hardware design;
wherein the first power report and the second power report are used to identity the one or more registers to be retimed.
17. A system, comprising:
a processor for synthesizing a first hardware design, generating a first power report for the synthesized first hardware design, altering the first hardware design, synthesizing the altered hardware design, generating a second power report for the synthesized altered hardware design, and optimizing the altered hardware design utilizing the first power report and the second power report;
wherein the system is operable such that the first power report and the second power report are compared for determining one or more registers that have increased in power usage from the first hardware design to the altered hardware design.
18. The system of claim 17 , wherein the processor remains in communication with memory via a bus.