Three dimensional structure memory
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
1 . An integrated circuit structure comprising:
a first substrate comprising a first surface having interconnect contacts and a second surface, wherein the second surface is opposite said first surface of the first substrate;
a second substrate comprising a first surface having interconnect contacts and a second surface, wherein the second surface is opposite said first surface of the second substrate;
the first and second substrates are stacked; and,
at least one of the first and second substrates is a thinned substrate, wherein the second surface of said thinned substrate is a polished surface.
2 . The integrated circuit structure of claim 1 , wherein surfaces of the first and second substrates are bonded, wherein a major portion of at least one of the surfaces is bonded.
3 . The integrated circuit structure of claim 1 , wherein the thinned substrate is caused to have a thickness of about 50 microns or less.
4 . The integrated circuit structure of claim 1 , wherein said polished surface is caused to be a CMP polished surface.
5 . The integrated circuit structure of claim 1 , wherein a plurality of signal paths are formed between the interconnect contacts of at least one surface of the first substrate and at least one surface of the second substrate.
6 . The integrated circuit structure of claim 1 , wherein at least one interconnection is formed between the first and second substrates.
7 . The integrated circuit structure of claim 1 , wherein a dielectric layer is deposited on the polished surface of the thinned substrate.
8 . An integrated circuit structure comprising:
a first substrate comprising a first surface having interconnect contacts and a second surface, wherein the second surface is opposite said first surface of the first substrate;
a second substrate comprising a first surface having at least one integrated circuit formed thereon and a second surface, wherein the second surface is opposite said first surface of the second substrate; and
at least one interconnection between at least one of the interconnection contacts and one of the at least one integrated circuits;
wherein at least one of the first and second substrates is a thinned substrate, and wherein the second surface of said thinned substrate is a polished surface; and
wherein the first and second substrates are stacked
9 . The integrated circuit structure of claim 8 , wherein one or more bonds join one of the surfaces of the first substrate and one of the surfaces of the second substrate to provide joined surfaces, thereby joining at least a major portion of the surface of one of said joined surfaces.
10 . An integrated circuit structure comprising:
a first substrate having topside and bottomside surfaces, wherein the topside surface of the first substrate has interconnect contacts;
a second substrate having topside and bottomside surfaces, wherein at least one of the topside and the bottomside surfaces of the second substrate has interconnect contacts;
wherein the first and second substrates are stacked; and
wherein at least one of the first and second substrates is a thinned substrate, and wherein the bottomside surface of said thinned substrate is a polished surface.
11 . The integrated circuit structure of claim 10 , wherein a majority of the surface of one of the surfaces of first substrate is bonded to one of the surfaces of the second substrate.
12 . An integrated circuit structure comprising:
a first substrate having topside and bottomside surfaces, wherein the topside surface of the first substrate has interconnect contacts;
a second substrate having topside and bottomside surfaces, wherein the topside of the second substrate has at least one integrated circuit formed thereon;
wherein the first and second substrates are stacked; and
wherein at least one of the first and second substrates is a thinned substrate, and wherein the bottomside of said thinned substrate is a polished surface.
13 . The integrated circuit structure of claim 12 , wherein a majority of the surface of one of the topside and bottomside surfaces of first substrate is bonded to one of the topside and bottomside surfaces of the second substrate.
14 . The integrated circuit structure of claim 1 , wherein at least one of the first and second substrates is substantially flexible, and comprises a dielectric layer with a tensile stress of about 5×10 8 dynes/cm 2 or less.
15 . The integrated circuit structure of claim 8 , wherein at least one of the first and second substrates is substantially flexible, and comprises a dielectric layer with a tensile stress of about 5×10 8 dynes/cm 2 or less.
16 . The integrated circuit structure of claim 10 , wherein at least one of the first and second substrates is substantially flexible, and comprises a dielectric layer with a tensile stress of about 5×10 8 dynes/cm 2 or less.
17 . The integrated circuit structure of claim 12 , wherein at least one of the first and second substrates is substantially flexible, and comprises a dielectric layer with a tensile stress of about 5×10 8 dynes/cm 2 or less.
18 . The integrated circuit structure of claim 8 , wherein surfaces of the first and second substrates are bonded, and wherein a major portion of at least one of the surfaces is bonded.
19 . The integrated circuit structure of claim 8 , wherein the thinned substrate is caused to have a thickness of about 50 microns or less.
20 . The integrated circuit structure of claim 8 , wherein said polished surface is caused to be a CMP polished surface.
21 . The integrated circuit structure of claim 8 , wherein a plurality of signal paths are formed between the interconnect contacts of at least one surface of the first substrate and at least one surface of the second substrate.
22 . The integrated circuit structure of claim 8 , wherein at least one interconnection is formed between the first and second substrates.
23 . The integrated circuit structure of claim 8 , wherein a dielectric layer is deposited on the polished second surface of the thinned substrate.
24 . The integrated circuit structure of claim 10 , wherein surfaces of the first and second substrates are bonded, and wherein a major portion of at least one of the surfaces is bonded.
25 . The integrated circuit structure of claim 10 , wherein the thinned substrate is caused to have a thickness of about 50 microns or less.
26 . The integrated circuit structure of claim 10 , wherein said polished surface is caused to be a CMP polished surface.
27 . The integrated circuit structure of claim 10 , wherein a plurality of signal paths are formed between the interconnect contacts of at least one surface of the first substrate and at least one surface of the second substrate.
28 . The integrated circuit structure of claim 10 , wherein at least one interconnection is formed between the first and second substrates.
29 . The integrated circuit structure of claim 10 , wherein a dielectric layer is deposited on the polished second surface of the thinned substrate.
30 . The integrated circuit structure of claim 12 , wherein surfaces of the first and second substrates are bonded, and wherein a major portion of at least one of the surfaces is bonded.
31 . The integrated circuit structure of claim 12 , wherein the thinned substrate is caused to have a thickness of about 50 microns or less.
32 . The integrated circuit structure of claim 12 , wherein said polished surface is caused to be a CMP polished surface.
33 . The integrated circuit structure of claim 12 , wherein a plurality of signal paths are formed between the interconnect contacts of at least one surface of the first substrate and at least one surface of the second substrate.
34 . The integrated circuit structure of claim 12 , wherein at least one interconnection is formed between the first and second substrates.
35 . The integrated circuit structure of claim 12 , wherein a dielectric layer is deposited on the polished second surface of the thinned substrate.
36 . An integrated circuit structure comprising:
a plurality of substrates comprising a first surface having at least one integrated circuit formed thereon and a second surface, wherein the second surface is opposite said first surface, and wherein at least one of the substrates is a thinned substrate;
wherein the plurality of substrates are stacked, wherein at least two of the substrates have facing surfaces positioned in one of the following positions: first surface facing second surface; first surface facing first surface; and second surface facing second surface; and
wherein at least one of the stacked substrates is a thinned substrate, and wherein the second surface of said thinned substrate is a polished surface.
37 . The integrated circuit structure of claim 36 , wherein the thinned substrate is caused to have a thickness of about 50 microns or less.
38 . The integrated circuit structure of claim 36 , wherein the polished surface is a Chemical Mechanical Polished surface.
39 . An integrated circuit structure comprising:
a first substrate comprising a first surface having interconnect contacts and a second surface, wherein the second surface is opposite said first surface of the first substrate;
at least one substrate comprising a first surface having at least one integrated circuit formed thereon and a second surface, wherein the second surface is opposite said first surface;
wherein at least one of the substrates is a thinned substrate and the second surface of said thinned substrate is caused to have a polished surface; and
wherein the first substrate and the at least one substrate are stacked, and wherein at least two of the substrates have facing surfaces positioned in one of the following positions: first surface facing second surface; first surface facing first surface; and second surface facing second surface.
40 . An integrated circuit structure comprising:
at least a plurality of stacked substrates each comprising a first surface having at least one integrated circuit formed thereon and a second surface, wherein the second surface is opposite said first surface;
wherein at least one of the stacked substrates is a thinned substrate, and wherein the second surface of said thinned substrate is caused to have a polished surface.
41 . The integrated circuit structure of claim 40 , wherein the thinned substrate is caused to have a thickness of about 50 microns or less.
42 . The integrated circuit structure of claim 40 , wherein the polished surface is a Chemical Mechanical Polished surface.