Semiconductor memory device
View Patent ↗A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.
1. A method for a semiconductor memory device which comprises a memory cell array, an address control circuit block configured to perform an access control to the memory cell array, a data I/O circuit block configured to transmit and receive data to and from the memory cell array, and a mode register, the method comprising:
setting first mode information into the mode register;
deactivating each of the address control circuit block and the data I/O circuit block in response to the first mode information;
changing a content of the mode register from the first mode information to second mode information; and
activating one of the address control circuit block and the data I/O circuit block while keeping the other of the address control circuit block and the data I/O circuit block deactivated in response to the second mode information.
2. The method as claimed in claim 1 , wherein in response to the second mode information, the data I/O circuit block is activated while the address control circuit block is kept deactivated.
3. The method as claimed in claim 1 , wherein the semiconductor memory device further comprises a main power supply wiring configured to supply a power voltage, a first pseudo power supply wiring configured to correspond to the address control circuit block and a second pseudo power supply wiring configured to correspond to the data I/O circuit block, and the deactivating each of the address control circuit block and the data I/O circuit block includes disconnecting each of the first and second pseudo power supply wiring from the main power supply wiring and the activating the one of the address control circuit block and the data I/O circuit block includes connecting a corresponding one of the first and second pseudo power supply wiring to the main power supply wiring.
4. The method as claimed in claim 3 , further comprising performing an ODT operation in response to the second mode information.
5. The method as claimed in claim 3 , further comprising performing an OCD-impedance adjacent operation in response to the second mode information.
6. The method as claimed in claim 2 , wherein the semiconductor memory device further comprises a main power supply wiring configured to supply a power voltage, a first pseudo power supply wiring configured to correspond to the address control circuit block and a second pseudo power supply wiring configured to correspond to the data I/O circuit block, and the deactivating each of the address control circuit block and the data I/O circuit block includes disconnecting each of the first and second pseudo power supply wiring from the main power supply wiring and the activating data I/O circuit block includes connecting the second pseudo power supply wiring to the main power supply wiring.
7. The method as claimed in claim 6 , further comprising performing an ODT operation in response to the second mode information.
8. The method as claimed in claim 6 , further comprising performing an OCD-impedance adjacent operation in response to the second mode information.