Method for manufacturing a semiconductor device
View Patent ↗A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is a semiconductor device of a super-junction structure, including: a gate electrode filled in a trench formed on a semiconductor substrate; a gate wiring metal forming a surface layer; and a gate electrode plug connecting between the gate electrode and the gate wiring metal. Thus, a polysilicon layer necessary for the conventional typical power MOSFET is unnecessary. That is, column regions of an element active portion and an outer peripheral portion can be formed under the same conditions. As a result, it is possible to improve an element breakdown voltage as compared with the conventional one.
1. A manufacturing method for a semiconductor device, comprising:
forming a semiconductor layer of a first conductivity type on a semiconductor substrate the semiconductor layer including an element active portion and a peripheral portion that is formed in an outer periphery of the element active portion;
forming a first trench and a second trench which are mutually connected in the semiconductor layer, the first trench being formed in the element active portion and the second trench being formed in the peripheral portion;
forming a gate electrode in the first trench and a gate electrode extraction portion in the second trench, the gate electrode and the gate electrode extraction portion being mutually connected;
forming a first column region of a second conductivity type in the element active portion in the semiconductor layer and a second column region of the second conductivity type in the peripheral portion in the semiconductor layer after forming the gate electrode in the first trench and the gate electrode extraction portion in the second trench, each of the first and second column regions having a columnar structure that is formed at a position deeper than the first and second trenches;
forming an interlayer insulating film over the semiconductor layer, the gate electrode and the gate electrode extraction portion;
forming a contact hole passing through the interlayer insulating film and protecting into the gate electrode extraction portion;
forming a gate electrode plug using a conductor filled in the contact hole; and
forming a gate wiring metal connected with the gate electrode plug over the interlayer insulating film.
2. The manufacturing method for a semiconductor device according to claim 1 , wherein the gate electrode and the gate electrode extraction portion are formed from a polysilicon layer.
3. The manufacturing method for a semiconductor device according to claim 1 , wherein the gate electrode and the gate electrode extraction portion have substantially a same depth as one another.
4. The manufacturing method for a semiconductor device according to claim 1 , wherein a portion of the gate electrode extraction portion is formed with a larger width than a width of the gate electrode.
5. The manufacturing method for a semiconductor device according to claim 1 , wherein the first column region and the second column region have substantially a same depth as one another.
6. The manufacturing method for a semiconductor device according to claim 1 , wherein the contact hole is defined as a first contact hole, the semiconductor device further comprising;
forming a base region of the second conductivity type in an upper portion of the semiconductor layer; and
forming a source region of the first conductivity type in an upper portion of the base region,
wherein the step of forming a contact hole further comprises forming a second contact hole passing through the interlayer insulating film and the source region and projecting into the base region,
the step of forming a gate electrode plug further comprises forming a source electrode plug filled in the second contact hole; and
the step of forming a gate wiring metal further comprises forming a source wiring metal connected with the source electrode plug over the interlayer insulating film.
7. The manufacturing method for a semiconductor device according to claim 6 , wherein the first contact hole and the second contact hole have substantially a same depth as one another.
8. The manufacturing method for a semiconductor device according to claim 1 , further comprising:
forming a zener diode coupled between the gate wiring metal and the source wiring metal.
9. The manufacturing method for a semiconductor device according to claim 8 , wherein the zener diode is formed from the polysilicon layer from which the gate electrode and the gate electrode extraction portion are formed.