Sub-threshold CMOS temperature detector
A CMOS temperature detection circuit includes a start-up circuit for generating a start-up voltage (VN), and a proportional to absolute temperature (PTAT) current generator coupled to the start-up circuit for generating a PTAT current. The start-up voltage turns on the PTAT current generator, and the PTAT current generator uses the sub-threshold characteristics of CMOS to generate the PTAT current. A PTAT voltage generator coupled to the PTAT current generator receives the PTAT current and generates a PTAT voltage and an inverse PTAT voltage (VBE). A comparator circuit coupled to the voltage generator compares the inverse PTAT voltage to first and second alarm limits, which are defined using the generated PTAT voltage, and generates an alarm signal based on the comparison results.
1. A CMOS temperature detection circuit, comprising:
a start-up circuit for generating a start-up voltage;
a proportional to absolute temperature (PTAT) current generator formed using CMOS technology, coupled to the start-up circuit, for generating a PTAT current, wherein the start-up voltage turns on the PTAT current generator, and wherein the PTAT current generator uses the sub-threshold characteristics of the CMOS technology to generate the PTAT current;
a PTAT voltage generator coupled to the PTAT current generator that receives the PTAT current and generates an inverse PTAT voltage (VBE) and a PTAT voltage, wherein first and second alarm values are derived from the PTAT voltage; and
a comparator circuit coupled to the voltage generator for comparing the inverse PTAT voltage to the first and second alarm values, respectively, and generating an alarm signal based on the comparison results.
2. The CMOS temperature detection circuit of claim 1 , wherein the start-up circuit comprises:
a first PMOS transistor having a source connected to a first power supply;
a first NMOS transistor having a drain connected to a drain of the first PMOS transistor at a first node, a source connected to a second power supply, and a gate connected to the second power supply; and
a second PMOS transistor having a source connected to the first power supply, and a gate connected to the drains of the first NMOS transistor and the first PMOS transistor at the first node.
3. The CMOS temperature detection circuit of claim 2 , wherein the first power supply has a value of about 0.9v and the second power supply is a ground.
4. The CMOS temperature detection circuit of claim 2 , wherein a size of the first NMOS transistor is larger than that of the first PMOS transistor.
5. The CMOS temperature detection circuit of claim 2 , wherein a leakage current of the first NMOS transistor is greater than a leakage current of the first PMOS transistor.
6. The temperature detection circuit of claim 2 , wherein the PTAT current generator comprises:
a third PMOS transistor having a source connected to the first power supply;
a fourth PMOS transistor having a source connected to the first power supply, a gate connected to a gate of the third PMOS transistor, and a drain connected to its gate;
a second NMOS transistor having a source connected to the second power supply, a drain connected to a drain of the third PMOS transistor, and a gate connected to the drain of the third PMOS transistor;
a third NMOS transistor having a source connected to the second power supply, a drain connected to the drain of the fourth PMOS transistor, and a gate connected to a drain of the second NMOS transistor; and
a resistor connected between the third PMOS transistor and the second NMOS transistor.
7. The temperature detection circuit of claim 2 , wherein the PTAT current generator comprises:
a third PMOS transistor having a source connected to the first power supply;
a fourth PMOS transistor having a source connected to the first power supply and a gate connected to a gate of the third PMOS transistor;
a second NMOS transistor having a drain connected to a drain of the third PMOS transistor, a source connected to the second power supply, and a gate connected to its drain;
a third NMOS transistor having a source connected to the second power supply, a drain connected to a drain of the fourth PMOS transistor, and a gate connected to the gate of the second NMOS transistor; and
a shunt resistor connected between the third NMOS transistor and the second power supply.
8. The temperature detection circuit of claim 7 , wherein the shunt resistor has a value of 200 kΩ.
9. The temperature detection circuit of claim 7 , wherein the PTAT voltage generator comprises:
a fifth PMOS transistor having a source connected to the first power supply and a gate connected to the gates of the third and fourth PMOS transistors;
a sixth PMOS transistor having a source connected to the first power supply and a gate connected to the gates of the third and fourth PMOS transistors;
a fifth PMOS transistor having a source connected to the first power supply and a gate connected to the gates of the third and fourth PMOS transistors;
a first resistor connected between a drain of the fifth PMOS transistor and the second power supply for defining the first alarm value;
a second resistor connected between a drain of the sixth PMOS transistor and the second power supply for defining the second alarm value; and
a bi-polar junction transistor (BJT) having an emitter connected to a drain of the seventh PMOS transistor, a base connected to the second power supply, and a collector also connected to the second power supply.
10. The temperature detection circuit of claim 9 , wherein the comparator comprises:
a first op amp having a positive terminal connected to the drain of the seventh PMOS transistor and a negative terminal connected to the node between the fifth PMOS transistor and the first resistor;
a second op amp having a positive terminal connected to the drain of the seventh PMOS transistor, and a negative terminal connected to the node between the sixth PMOS transistor and the second resistor; and
a XOR gate that receives the outputs of the first and second op amps, and outputs the alarm signal.
11. The temperature detection circuit of claim 9 , wherein:
a first current moves from the fifth PMOS transistor to the first resistor, generating the first alarm value at a node between the fifth PMOS transistor and the first resistor; and
a second current moves from the sixth PMOS transistor to the second resistor, generating the second alarm value at a node between the sixth PMOS transistor and the second resistor.
12. The temperature detection circuit of claim 11 , wherein the first and second resistors and have different sizes to define different first and second alarm values.
13. The temperature detection circuit of claim 12 , wherein the first resistor has a value of 1200 kΩ and the second resistor has a value of 500 kΩ.
14. A CMOS temperature detection circuit, comprising:
a start-up circuit for generating a start-up voltage, the start-up circuit including:
a first PMOS transistor having a source connected to a first power supply;
a first NMOS transistor having a drain connected to a drain of the first PMOS transistor at a first node, a source connected to a second power supply, and a gate connected to the second power supply; and
a second PMOS transistor having a source connected to the first power supply, and a gate connected to the drains of the first NMOS transistor and the first PMOS transistor at the first node;
a proportional to absolute temperature (PIAT) current generator formed using CMOS technology, coupled to the start-up circuit, for generating a PTAT current, wherein the start-up voltage turns on the PTAT current generator, and wherein the PTAT current generator uses the sub-threshold characteristics of the CMOS technology to generate the PTAT current, wherein the PTAT current generator comprises:
a third PMOS transistor having a source connected to the first power supply;
a fourth PMOS transistor having a source connected to the first power supply and a gate connected to a gate of the third PMOS transistor, wherein the PTAT current is generated at a node between the gates of the third and fourth PMOS transistors;
a second NMOS transistor having a drain connected to a drain of the third PMOS transistor, a source connected to the second power supply, and a gate connected to its drain;
a third NMOS transistor having a source connected to the second power supply, a drain connected to a drain of the fourth PMOS transistor, and a gate connected to the gate of the second NMOS transistor; and
a shunt resistor connected between the third NMOS transistor and the second power supply;
a PTAT voltage generator coupled to the PTAT current generator that receives the PTAT current and generates an inverse PTAT voltage and a PTAT voltage, wherein first and second alarm values are defined using the PTAT voltage; and
a comparator circuit coupled to the voltage generator for comparing the inverse PTAT voltage to the first and second alarm values, respectively, and generating an alarm signal based on the comparison results.
15. The CMOS temperature detection circuit of claim 14 , a size of the first NMOS transistor is larger than that of the first PMOS transistor.
16. The temperature detection circuit of claim 14 , wherein the PTAT voltage generator comprises:
a fifth PMOS transistor having a source connected to the first power supply and a gate connected to the gates of the third and fourth PMOS transistors;
a sixth PMOS transistor having a source connected to the first power supply and a gate connected to the gates of the third and fourth PMOS transistors;
a seventh PMOS transistor having a source connected to the first power supply and a gate connected to the gates of the third and fourth PMOS transistors;
a first resistor connected between a drain of the fifth PMOS transistor and the second power supply for defining the first alarm value;
a second resistor connected between a drain of the sixth PMOS transistor and the second power supply for defining the second alarm value; and
a bi-polar junction transistor (BJT) having an emitter connected to a drain of the seventh PMOS transistor, a base connected to the second power supply, and a collector also connected to the second power supply.
17. The temperature detection circuit of claim 16 , wherein the comparator comprises:
a first op amp having a positive terminal connected to the drain of the seventh PMOS transistor and a negative terminal connected to the node between the fifth PMOS transistor and the first resistor;
a second op amp having a positive terminal connected to the drain of the seventh PMOS transistor, and a negative terminal connected to the node between the sixth PMOS transistor and the second resistor; and
a XOR gate that receives the outputs of the first and second op amps, and outputs the alarm signal.
18. The temperature detection circuit of claim 17 , wherein:
a first current moves from the fifth PMOS transistor to the first resistor, and the first alarm value is generated at a node between the fifth PMOS transistor and the first resistor; and
a second current moves from the sixth PMOS transistor to the second resistor, and the second alarm value is generated at a node between the sixth PMOS transistor and the second resistor.
19. The temperature detection circuit of claim 18 , wherein the comparator comprises:
a first op amp having a positive terminal connected to the drain of the seventh PMOS transistor and a negative terminal connected to the node between the fifth PMOS transistor and the first resistor;
a second op amp having a positive terminal connected to the drain of the seventh PMOS transistor, and a negative terminal connected to the node between the sixth PMOS transistor and the second resistor; and
a XOR gate that receives the outputs of the first and second op amps, and outputs the alarm signal.
20. A CMOS temperature detection circuit, comprising:
a start-up circuit for generating a start-up voltage, the start-up circuit including:
a first PMOS transistor having a source connected to a first power supply;
a first NMOS transistor having a drain connected to a drain of the first PMOS transistor at a first node, a source connected to a second power supply, and a gate connected to the second power supply; and
a second PMOS transistor having a source connected to the first power supply, and a gate connected to the drains of the first NMOS transistor and the first PMOS transistor at the first node;
a proportional to absolute temperature (PIAT) current generator formed using CMOS technology, coupled to the start-up circuit, for generating a PTAT current, wherein the start-up voltage turns on the PTAT current generator, and wherein the PTAT current generator uses the sub-threshold characteristics of the CMOS technology to generate the PTAT current, wherein the PTAT current generator includes:
a third PMOS transistor having a source connected to the first power supply;
a fourth PMOS transistor having a source connected to the first power supply and a gate connected to a gate of the third PMOS transistor, wherein the PIAT current is generated at a node between the gates of the third and fourth PMOS transistors;
a second NMOS transistor having a drain connected to a drain of the third PMOS transistor, a source connected to the second power supply, and a gate connected to its drain;
a third NMOS transistor having a source connected to the second power supply, a drain connected to a drain of the fourth PMOS transistor, and a gate connected to the gate of the second NMOS transistor; and
a shunt resistor connected between the third NMOS transistor and the second power supply;
a PTAT voltage generator coupled to the PTAT current generator that receives the PTAT current and generates an inverse PTAT voltage and a PTAT voltage, wherein first and second alarm values are derived using the PTAT voltage, wherein the PTAT voltage generator includes:
a fifth PMOS transistor having a source connected to the first power supply and a gate connected to the gates of the third and fourth PMOS transistors;
a sixth PMOS transistor having a source connected to the first power supply and a gate connected to the gates of the third and fourth PMOS transistors;
a seventh PMOS transistor having a source connected to the first power supply and a gate connected to the gates of the third and fourth PMOS transistors;
a first resistor connected between a drain of the fifth PMOS transistor and the second power supply for defining the first alarm value;
a second resistor connected between a drain of the sixth PMOS transistor and the second power supply for defining the second alarm value; and
a bi-polar junction transistor (BJT) having an emitter connected to a drain of the seventh PMOS transistor, a base connected to the second power supply, and a collector also connected to the second power supply; and
a comparator circuit coupled to the voltage generator for comparing the inverse PTAT voltage to the first and second alarm values, respectively, and generating an alarm signal based on the comparison results.