Semiconductor device and method for manufacturing the same
An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
1. A semiconductor device including a thin film transistor, the thin film transistor comprising:
a gate electrode layer;
a gate insulating layer over the gate electrode layer;
a semiconductor layer over the gate insulating layer;
a first n-type buffer layer and a second n-type buffer layer over the semiconductor layer;
a source electrode layer over the first n-type buffer layer, and a drain electrode layer over the second n-type buffer layer;
a third buffer layer between the semiconductor layer and the first n-type buffer layer; and
a fourth buffer layer between the semiconductor layer and the second n-type buffer layer,
wherein each of the semiconductor layer, the first n-type buffer layer and the second n-type buffer layer comprises oxide semiconductor containing indium, gallium, and zinc,
wherein each of the first n-type buffer layer and the second n-type buffer layer has higher carrier concentration than the semiconductor layer,
wherein each of the first n-type buffer layer and the second n-type buffer layer contains one selected from the group consisting of magnesium, aluminum and titanium, and
wherein each of the third buffer layer and the fourth buffer layer has a carrier concentration which is higher than that of the semiconductor layer and lower than that of each of the first n-type buffer layer and the second n-type buffer layer.
2. The semiconductor device according to claim 1 , wherein each of the first n-type buffer layer and the second n-type buffer layer contains an impurity element imparting n-type conductivity.
3. The semiconductor device according to claim 1 , wherein a carrier concentration of the semiconductor layer is less than 1×10 17 atoms/cm 3 and each carrier concentration of the first n-type buffer layer and the second n-type buffer layer is 1×10 18 atoms/cm 3 or higher.
4. The semiconductor device according to claim 1 , wherein the source electrode layer and the drain electrode layer contain titanium.
5. The semiconductor device according to claim 1 , further comprising an insulating layer over the source electrode layer and the drain electrode layer, wherein the insulating layer is in contact with an upper surface of the source electrode layer, an upper surface of the drain electrode layer, and a region of the semiconductor layer between the source electrode layer and the drain electrode layer.
6. The semiconductor device according to claim 1 ,
wherein the gate electrode layer comprises copper,
wherein the gate insulating layer comprises a first layer, a second layer and a third layer, and
wherein each of the first layer, the second layer and the third layer comprises silicon and nitrogen.
7. A semiconductor device including a thin film transistor, the thin film transistor comprising:
a gate electrode layer;
a gate insulating layer over the gate electrode layer;
a semiconductor layer over the gate insulating layer;
a first n-type buffer layer and a second n-type buffer layer over the semiconductor layer;
a source electrode layer over the first n-type buffer layer, and a drain electrode layer over the second n-type buffer layer;
a third buffer layer between the semiconductor layer and the first n-type buffer layer; and
a fourth buffer layer between the semiconductor layer and the second n-type buffer layer,
wherein each of the semiconductor layer, the first n-type buffer layer and the second n-type buffer layer comprises oxide semiconductor containing indium, gallium, and zinc,
wherein a region of the semiconductor layer between the first n-type buffer layer and the second n-type buffer layer is thinner than a region of the semiconductor layer under the first n-type buffer layer and a region of the semiconductor layer under the second n-type buffer layer,
wherein each of the first n-type buffer layer and the second n-type buffer layer has higher carrier concentration than the semiconductor layer,
wherein each of the first n-type buffer layer and the second n-type buffer layer contains one selected from the group consisting of magnesium, aluminum and titanium, and
wherein each of the third buffer layer and the fourth buffer layer has a carrier concentration which is higher than that of the semiconductor layer and lower than that of each of the first n-type buffer layer and the second n-type buffer layer.
8. The semiconductor device according to claim 7 , wherein each of the first n-type buffer layer and the second n-type buffer layer contains an impurity element imparting n-type conductivity.
9. The semiconductor device according to claim 7 , wherein a carrier concentration of the semiconductor layer is less than 1×10 17 atoms/cm 3 and each carrier concentration of the first n-type buffer layer and the second n-type buffer layer is 1×10 18 atoms/cm 3 or higher.
10. The semiconductor device according to claim 7 , wherein the source electrode layer and the drain electrode layer contain titanium.
11. The semiconductor device according to claim 7 , further comprising an insulating layer over the source electrode layer and the drain electrode layer, wherein the insulating layer is in contact with an upper surface of the source electrode layer, an upper surface of the drain electrode layer, and a region of the semiconductor layer between the source electrode layer and the drain electrode layer.
12. The semiconductor device according to claim 7 ,
wherein the gate electrode layer comprises copper,
wherein the gate insulating layer comprises a first layer, a second layer and a third layer, and
wherein each of the first layer, the second layer and the third layer comprises silicon and nitrogen.