High-Speed Low-Power Differential Receiver
A low-voltage differential communication system includes a low- and programmable-swing voltage-mode transmitter that delivers a low-voltage differential signal to a receiver via differential channel. The receiver employs two input transistors, each in a common-gate configuration, to recover the low-voltage differential signal. A current source in the receiver biases the input transistors such that their source voltages are nominally biased at the common-mode voltage of the differential signal, and their gate-source voltages remain essentially constant with common-mode-voltage fluctuations.
1 . An amplifier comprising:
a voltage divider having a common-mode-voltage tap between differential first and second inputs;
a first transistor having a first current-handling terminal, coupled to the first input, and a first control terminal;
a second transistor having a second current-handling terminal, coupled to the second input, and a second control terminal coupled to the first control terminal;
a third transistor having a third current-handling terminal, coupled to the tap, a third control terminal coupled to the first control terminal, and a fourth current-handling terminal; and
a current source having a bias-current output node coupled to the fourth current-handling terminal to provide a bias current through the third transistor.
2 . The amplifier of claim 1 , wherein the first, second, and third transistors are nMOS transistors.
3 . The amplifier of claim 1 , wherein the bias current through the fourth current-handling terminal of the third transistor fixes a voltage between the tap and the first and second control terminals.
4 . The amplifier of claim 1 , wherein the current source includes a replica transistor having a replica control terminal and a replica current-handling terminal.
5 . The amplifier of claim 4 , wherein the current source is to hold the replica current-handling terminal at a reference voltage.
6 . The amplifier of claim 5 , wherein the reference voltage approximates a common-mode voltage on the tap.
7 . The amplifier of claim 1 , further comprising a diode having an anode connected to the first input and a cathode connected to a ground terminal at a ground potential, wherein the diode exhibits a threshold voltage.
8 . The amplifier of claim 7 , wherein a common-mode voltage on the tap is referenced to the ground potential, and wherein the common-mode voltage is less than half the threshold voltage.
9 . A communication system comprising:
a differential transmitter having first and second transmitter nodes to convey a differential signal referenced to a ground node at ground potential;
first and second diodes each having an anode connected to one of the first and second transmitter nodes and a cathode connected to the ground node, wherein each of the first and second diodes conducts current from the anode to the cathode when the anode-to-cathode voltage exceeds a diode threshold voltage, and wherein the differential signal exhibits a common-mode voltage, referenced to the ground potential, that is less than half of the diode threshold voltage; and
a differential receiver having:
a voltage divider having a common-mode-voltage tap between the first and second transmitter nodes;
a first transistor having a first current-handling terminal, coupled to the first transmitter node, and a first control terminal;
a second transistor having a second current-handling terminal, coupled to the second transmitter node, and a second control terminal coupled to the first control terminal;
a third transistor having a third current-handling terminal, coupled to the tap, a third control terminal coupled to the first control terminal, and a fourth current-handling terminal; and
a current source having a bias-current output node coupled to the fourth current-handling terminal to provide a bias current through the third transistor.
10 . The system of claim 9 , wherein the first, second, and third transistors are nMOS transistors.
11 . The system of claim 9 , wherein the bias current through the fourth current-handling terminal of the third transistor fixes a second voltage between the tap and the first and second control terminals.
12 . The system of claim 9 , wherein the current source includes a replica transistor similar to the first transistor and having a replica control terminal and a replica current-handling terminal.
13 . The amplifier of claim 12 , wherein the current source is to hold the replica current-handling terminal at a reference voltage.
14 . The amplifier of claim 13 , wherein the reference voltage approximates the common-mode voltage.
15 . A method for receiving first and second complementary signals on respective complementary input pads and exhibiting a common-mode voltage, wherein each of the complementary input pads is coupled to a supply node via a respective diode that exhibits a diode threshold voltage, the method comprising:
biasing a source or emitter of each of a first and second n-type transistors to a reference voltage less than half of the diode threshold voltage and a gate or base of the first and second transistors to a gate-bias voltage above the reference voltage;
applying the first and second complementary signals to the sources or emitters of the respective first and second n-type transistors;
extracting the common-mode voltage from the first and second complementary signals; and
changing the gate-bias voltage with changes in the extracted common-mode voltage, wherein the gate-bias voltage rises and falls with the extracted common-mode voltage.
16 . The method of claim 15 , further comprising generating the gate-bias voltage by passing a bias current through a third transistor having a gate or base connected to the gate or base of the first and second n-type transistors.
17 . The method of claim 16 , further comprising passing a current through a replica of the first transistors to establish the bias current.
18 . An amplifier comprising:
complementary first and second inputs to receive a differential signal that exhibits a common-mode voltage;
a first transistor having a first current-handling terminal coupled to the first input, a second current-handling terminal, and a first control terminal;
a second transistor having a third current-handling terminal coupled to the second input, a fourth current-handling terminal, and a second control terminal coupled to the first control terminal;
means for biasing the first and third current-handling terminals at the common-mode voltage, and the first and second control terminals at a gate-bias voltage above the common-mode voltage; and
means for changing the gate-bias voltage with changes in the common-mode voltage.
19 . A computer-readable medium having stored thereon a data structure defining an amplifier, the data structure comprising:
first data representing a voltage divider having a common-mode-voltage tap between differential first and second inputs;
second data representing a first transistor having a first current-handling terminal, coupled to the first input, and a first control terminal;
third data representing a second transistor having a second current-handling terminal, coupled to the second input, and a second control terminal coupled to the first control terminal;
fourth data representing a third transistor having a third current-handling terminal, coupled to the tap, a third control terminal coupled to the first control terminal, and a fourth current-handling terminal; and
fifth data representing a current source having a bias-current output node coupled to the fourth current-handling terminal to provide a bias current through the third transistor.
20 . A receiver comprising:
complementary first and second differential inputs to receive a differential signal that exhibits a common-mode voltage;
complementary first and second signal paths that extend from the respective first and second differential inputs;
a differential amplifier having first and second amplifier inputs coupled to the respective first and second differential inputs via the first and second signal paths; and
common-mode rejection circuitry outside of the first and second differential signal paths.
21 . The receiver of claim 20 , further comprising a voltage divider extending between the first and second inputs and including a common-mode-voltage tap coupled to the common-mode rejection circuitry.
22 . The receiver of claim 20 , wherein the differential amplifier includes a first transistor and a second transistor, wherein the first amplifier input is a first source of the first transistor, and wherein the second amplifier input is a second source of the second transistor.
23 . The receiver of claim 22 , wherein the common-mode rejection circuitry includes a diode-connected third transistor, and wherein the first, second, and third transistors have interconnected gate terminals.