Adjustable write pulse generator within a chalcogenide memory device
View Patent ↗An adjustable write pulse generator is disclosed. The adjustable write pulse generator includes a band-gap reference current, a programmable ring oscillator, a frequency divider and a single pulse generator. The band-gap reference current circuit generates a well-compensated current over a predetermined range of temperatures needed to program a chalcogenide memory cell. The programmable ring oscillator generates a first set of continuous write “0” and write “1” pulse signals based on the well-compensated current. The frequency divider then divides the first set of continuous write “0” and write “1” pulse signals into a second set of continuous write “0” and write “1” pulse signals. The single pulse generator subsequently converts the second set of continuous write “0” and write “1” pulse signals into a single write “0” pulse signal or a single write “1” pulse signal when programming the chalcogenide memory cell.
1. An adjustable write pulse generator comprising:
a band-gap reference current circuit for generating a well-compensated current over a predetermined range of temperatures needed to program a chalcogenide memory cell;
a programmable ring oscillator for generating a first set of continuous write “0” and write “1” pulse signals based on said well-compensated current;
a frequency divider for dividing said first set of continuous write “0” and write “1” pulse signals into a second set of continuous write “0” and write “1” pulse signals; and
a single pulse generator for converting said second set of continuous write “0” and write “1” pulse signals into a single write “0” pulse signal or a single write “1” pulse signal when programming said chalcogenide memory cell.
2. The adjustable write pulse generator of claim 1 , wherein said adjustable write pulse generator further includes a control circuit for controlling the widths of said single write “0” or write “1” pulse signal.
3. The adjustable write pulse generator of claim 1 , wherein said control circuit allows said single write “0” pulse signal to have two different pulse widths and said single write “1” pulse signal to have four different pulse widths.
4. The adjustable write pulse generator of claim 1 , wherein said frequency divider further generates a plurality of clock signals for shaping said write “1” pulse signal at a write head.
5. The adjustable write pulse generator of claim 1 , wherein an output clock of said programmable ring oscillator is adjustable according to a specific process technology of said chalcogenide memory cell.