Clocking analog components operating in a digital system
View Patent ↗In one example, a clock generation component is configured to receive a master clock and generate a plurality of clock signals that are shifted relative to one another for a chip having an analog domain and a digital domain. A first selection component is configured to select a first one of the generated clock signals and drive the digital domain according to the first clock signal. A second selection component is configured to select a second one of the generated clock signals that is shifted relative to the first clock signal currently used to drive the digital domain for driving an analog component of the analog domain.
1. An apparatus, comprising:
a chip having an analog domain and a digital domain;
a clock generation component configured to receive a master clock and generate a plurality of clock signals that are shifted relative to one another;
a first selection component coupled to the clock generation component, the first selection component configured to select a first one of the generated clock signals and drive the digital domain according to the first clock signal;
a second selection component coupled to the clock generation component, the second selection component configured to select a second one of the generated clock signals that is shifted relative to the first clock signal and configured to drive an analog component of the analog domain; and
an inverter coupled with the analog component, the inverter configured to invert the second clock signal to generate an inverted clock signal to feed to the analog component, wherein a delay between operating edges of the inverted clock signal and the first clock signal is greater than a delay between operating edges of the selected clock signals.
2. The apparatus of claim 1 , wherein the analog component comprises an Analog to Digital Converter (ADC), a Digital to Analog Converter (DAC), or a switching capacitor amplifier coupled to the second selection component, and wherein the analog component is timed to operate on analog data in-between pulses that time operation of digital components of the chip.
3. The apparatus of claim 2 , further comprising:
a synchronization component coupled to the analog component, the synchronization component configured to re-clock data generated by the analog component according to the first clock signal.
4. The apparatus of claim 1 , wherein there are N+1 generated clock signals, and wherein a delay between any one of the generated clock signals and an immediately preceding clock signal is 1/Nth the amount of delay between at least delay one of the clock signals and a most delayed one of the clock signals.
5. The apparatus of claim 1 , further comprising:
a third selection component coupled to the clock generation component, the third selection component configured to select a third one of the generated clock signals that is shifted relative to the first clock signal currently used to drive the digital domain and drive an additional analog component of the analog domain according to the third clock signal while the analog component is still being driven according to the second clock signal.
6. The apparatus of claim 5 , further comprising:
a fourth selection component coupled to the second or third selection component, the fourth selection component configured to receive a plurality of other clock signals in addition to the second clock signal and select from the received clock signals for driving the analog component.
7. The apparatus of claim 1 , wherein the second clock signal is delayed with respect to the first clock signal.
8. The apparatus of claim 1 , further comprising:
a divider coupled to the analog component, the divider configured to receive the second clock signal, perform a divide operation thereon, and feed a result of the divide operation to the analog component.
9. The apparatus of claim 1 , further comprising:
a controller coupled to the second selection component, the controller configured to compare an output of the analog component that is driven according to the second clock signal to a stored value;
the controller configured to determine whether a variation between the output and the stored value is greater than a threshold; and
the controller configured to, if the variation is greater than the threshold, causes the second selection component to vary an output thereby causing the analog component to operate according to a changed amount of skew relative to the first clock signal used by the digital domain.
10. The apparatus of claim 1 , further comprising:
a controller coupled to the second selection component, the controller configured to monitor the chip and determine whether a current condition is outside a set range; and
the controller configured to, if the current condition is outside the set range, cause the second selection component to vary an output thereby causing the analog component to operate according to a changed amount of skew relative to the first clock signal used by the digital domain.
11. A method, comprising:
generating a plurality of clock signals based on a master clock, wherein the generated clock signals are shifted relative to one another;
operating a digital domain of a chip using a first one of the generated clock signals;
operating an analog component of an analog domain of the chip using a second different one of the generated clock signals;
wherein the analog component processes data at instants of inactivity in the digital domain;
inverting the second clock signal to generate an inverted clock signal; and
feeding the inverted clock signal to the analog component, wherein a delay between operating edges of the inverted clock signal and the first clock signal is greater than a delay between operating edges of the selected clock signals.
12. The method of claim 11 , wherein there are N+1 generated clock signals, and wherein a delay between any one of the generated clock signals and an immediately preceding clock signal is 1/Nth the amount of delay between a least delayed one of the clock signals and a most delayed one of the clock signals.
13. The method of claim 11 , further comprising re-clocking data generated by the analog component according to the first clock signal.
14. The method of claim 11 , further comprising:
dividing the second clock signal; and
feeding the inverted clock signal to the analog component for clocking operation of the same.
15. The method of claim 11 , further comprising:
dividing the second clock signal;
inverting the dividing clock signal; and
feeding the inverted clock signal to the analog component for clocking operation of the same.
16. The method of claim 11 , wherein the second clock signal is delayed with respect to the first clock signal.
17. An apparatus, comprising:
a chip having a digital domain and an analog domain;
a programmable delay line configured to receive a master clock and generate a plurality of clock signals that are shifted relative to one another;
a first multiplexer coupled to the programmable delay line, the first multiplexer configured to select between the generated clock signals and pass such selected clock signal to the digital domain for clocking operation of a digital component operating therein;
a second multiplexer coupled to the programmable delay line, the second multiplexer configured to select between the generated clock signals and pass such selected clock signal to the analog domain for clocking operation of an analog component operating therein; and
an inverter coupled with the analog component, the inverter configured to invert the second clock signal to generate an inverted clock signal to feed to the analog component, wherein a delay between operating edges of the inverted clock signal and the first clock signal is greater than a delay between operating edges of the selected clock signals.
18. The apparatus of claim 17 , wherein the analog component comprises an Analog to Digital Converter (ADC) or a Digital to Analog Converter (DAC) coupled to the second multiplexer.