IP Library Granted Patent US 8,456,235
Granted Patent B2
US 8,456,235 · App. 12/535,184 · Granted Jun 4, 2013

Regulator circuit

Inventors: Suguru Tachibana (Kawasaki, JP); Kenta Aruga (Kawasaki, JP); Tatsuo Kato (Kawasaki, JP)
Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 8,456,235
App. No.
12/535,184
Granted
Jun 4, 2013
Kind
B2
Abstract

The present invention is contrived to adopt a differential pair type amplifier circuit comprising a differential pair constituted by a first transistor receiving an input of a first signal and by a second transistor receiving an input of a third signal generated by outputting a second signal of which the voltage level is a power supply voltage. Elements requiring a matching are two transistors constituting the differential pair for the amplifier circuit. Because of this, the elements requiring a matching can be placed close to each other regardless of a layout between the amplifier circuits.

Claims (16)

1. A regulator circuit comprising:

a load driving amplifier including a differential pair and configured to output a second signal of a constant power supply voltage and supply a load current through a first output node of the load driving amplifier, the differential pair including a first transistor configured to receive an input of a first signal used as a reference and a second transistor configured to receive an input of a third signal generated on the basis of the second signal the first signal being a signal of a bandgap voltage;

a resistance voltage division circuit configured to generate the third signal from the second signal; and

a charging-use amplifier configured to charge a capacitance element through a second output node of the charging-use amplifier in a time period during which the load driving amplifier is in an off state, the capacitance element and the second output node of the charging-use amplifier being electrically connected to the first output node of the load driving amplifier.

2. The regulator circuit according to claim 1 , further comprising

an output stopping unit configured to stop an output of the second signal from the load driving amplifier during the time period in which the charging-use amplifier charges the capacitance element.

3. The regulator circuit according to claim 2 , wherein the time period is one immediately after turning electric power on.

4. The regulator circuit according to claim 1 , wherein

the charging-use amplifier comprises an electric current control unit for controlling an electric current flowing in the second transistor, in addition to substantially the same configuration as the load driving amplifier.

5. The regulator circuit according to claim 4 , wherein

the electric current control unit suppresses an increase of an electric current flowing in the second transistor with voltage applied thereto.

6. The regulator circuit according to claim 1 , further comprising

a discharge unit configured to respond to an over-charging in the capacitance element by making the capacitance element discharge a charged charge therein after completing a charging by the charging-use amplifier.

7. The regulator circuit according to claim 1 , wherein the load driving amplifier comprises a current source for making a sum of currents supplied by the differential pair constant.

8. The regulator circuit according to claim 1 , wherein

an amount of an electric current supplied by the charging-use amplifier is smaller than an amount of an electric current supplied by the load driving amplifier.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036055/0276 →
CORRECTIVE ASSIGNMENT TO INCLUDE A COMPLETE COPY OF THE ASSIGNMENT AND EXHIBIT A PREVIOUSLY RECORDED ON REEL 023352 FRAME 182. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 23, 2015
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 034807/0032 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Dec 30, 2014
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 034715/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024748/0328 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2009
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 023352/0182 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2009
From: TACHIBANA, SUGURU; ARUGA, KENTA; KATO, TATSUO
To: FUJITSU LIMITED
Reel/Frame 023095/0066 →
Priority Claims (1)
JP 2006-170741 · Jun 20, 2006 · national
Continuity (2)
Division 11589140 · Oct 30, 2006
Related Publication 20100156533A1 · Jun 24, 2010