Semiconductor device and method of manufacturing the same
View Patent ↗A method for manufacturing a semiconductor device includes forming an N-well and a P-well formed in a semiconductor substrate. An isolation layer may be formed in the semiconductor substrate. At least one dummy active pattern may be formed in a boundary area between the N-well and the P-well. A salicide blocking layer may be over the upper surface of the at least one dummy active pattern. A non-salicide region may be formed over the upper surface of the at least one dummy active pattern by carrying out a salicide process over the semiconductor substrate provided with the salicide blocking layer.
1. An apparatus comprising:
an N-well and a P-well formed in a semiconductor substrate;
an isolation layer formed in the semiconductor substrate to define active regions and field regions;
at least one dummy active pattern formed in a boundary area between the N-well and the P-well, wherein each dummy active pattern is formed in both the N-well and the P-well; and
a non-salicide region formed over the at least one dummy active pattern.
2. The apparatus of claim 1 , further comprising salicide regions formed in the active regions of the semiconductor substrate.
3. The apparatus of claim 1 , wherein the at least one dummy active pattern is made of silicon.
4. The apparatus of claim 2 , further comprising contacts formed by implanting impurity ions into the active regions.
5. The apparatus of claim 4 , wherein the salicide regions are formed over the upper surfaces of the contacts.
6. The apparatus of claim 1 , wherein the at least one dummy active pattern is formed in one region of the semiconductor substrate adjacent to a boundary between the N-well and the P-well.
7. The apparatus of claim 1 , wherein said each dummy active pattern is surrounded by and in direct contact with the isolation layer.
8. A method comprising:
forming an N-well and a P-well in a semiconductor substrate;
forming an isolation layer in the semiconductor substrate provided with the N-well and the P-well;
forming at least one dummy active pattern in a boundary area between the N-well and the P-well, wherein each dummy active pattern is formed in both the N-well and the P-well;
forming a salicide blocking layer over the upper surface of the at least one dummy active pattern; and
forming a non-salicide region over the upper surface of the at least one dummy active pattern by carrying out a salicide process over the semiconductor substrate provided with the salicide blocking layer.
9. The method of claim 8 , wherein the formation of the at least one dummy active pattern is carried out together with a patterning process to form the isolation layer.
10. The method of claim 9 , wherein the formation of the isolation layer includes:
forming a first photoresist pattern to form trenches to form the isolation layer;
forming the trenches by etching the semiconductor substrate using the first photoresist pattern; and
forming the isolation layer by filling the insides of the trenches with an oxide and removing the first photoresist pattern.
11. The method of claim 10 , wherein the formation of the first photoresist pattern is carried out so as not to expose one region of the semiconductor substrate adjacent to a boundary between the N-well and the P-well, in which the at least one dummy active pattern is formed.
12. The method of claim 8 , wherein the formation of the salicide blocking layer includes:
forming an oxide layer over the semiconductor substrate provided with the at least one dummy active pattern; and
forming the salicide blocking layer covering the upper surface of the at least one dummy active pattern by patterning the oxide film through a photography process and an etching process.
13. The method of claim 8 , wherein the formation of the non-salicide region includes:
depositing a metal from the group consisting of nickel and cobalt over the semiconductor substrate provided with the salicide blocking layer; and
forming the non-salicide region over the upper surface of the at least one dummy active pattern by preventing a salicide reaction between the metal and the at least one dummy active pattern by the salicide blocking layer during the salicide process.
14. The method of claim 13 , wherein salicide regions are formed over the upper surfaces of the active regions of the semiconductor substrate during the salicide process.
15. The method of claim 8 , wherein salicide process includes annealing.
16. The method of claim 8 , wherein said each dummy active pattern is surrounded by and in direct contact with the isolation layer.
17. An apparatus comprising:
an N-well and a P-well formed in at least one active region of a semiconductor substrate;
at least one dummy active pattern formed in a boundary area between the N-well and the P-well, wherein each dummy active pattern is formed in both the N-well and the P-well; and
a non-salicide region formed over the at least one dummy active pattern.
18. The apparatus of claim 17 , further comprising salicide regions formed in the active region of the semiconductor substrate.
19. The apparatus of claim 17 , wherein the at least one dummy active pattern is made of silicon.
20. The apparatus of claim 18 , further comprising contacts formed by implanting impurity ions into the active region.
21. The apparatus of claim 20 , wherein the salicide regions are formed over the upper surfaces of the contacts.
22. The apparatus of claim 17 , wherein the at least one dummy active pattern is formed in one region of the semiconductor substrate adjacent to a boundary between the N-well and the P-well.