IP Library Granted Patent US 8,319,205
Granted Patent B2
US 8,319,205 · App. 12/536,815 · Granted Nov 27, 2012

Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same

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Quick Facts
Patent No.
US 8,319,205
App. No.
12/536,815
Granted
Nov 27, 2012
Kind
B2
Abstract

Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.

Claims (9)

1. A nonvolatile nanotube memory cell comprising:

a nanotube field effect transistor comprising:

a first nanotube fabric article, the first nanotube fabric article comprising a semiconducting nanotube fabric and having a drain region and a source region in a spaced relation to one another, wherein the spaced relation defines a channel region in the first nanotube fabric article;

a gate node electrically coupled to the first nanotube fabric, wherein the gate node modulates the conductivity of the channel region to form or unform a first electrically conductive channel between the source and drain regions in response to a first electrical stimulus; and

a nanotube switching element comprising:

a second nanotube fabric article electrically coupled to the source region of the nanotube field effect transistor and an electrode;

the second nanotube fabric article forming or unforming a second electrically conductive channel between the source region and the electrode in response to a second electrical stimulus on at least the electrode;

wherein the forming of the first and second electrically conductive channels corresponds to at least a first memory state of the nanotube memory cell;

wherein the unforming of the first and second electrically conductive channels corresponds to at least a second memory state of the nanotube memory cell.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2021
From: SILICON VALLEY BANK
To: NANTERO, INC.
Reel/Frame 056790/0001 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Nov 11, 2020
From: NANTERO, INC.
To: SILICON VALLEY BANK
Reel/Frame 054383/0632 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2009
From: BERTIN, CLAUDE L.; RUECKES, THOMAS; MANNING, H. MONTGOMERY
To: NANTERO, INC.
Reel/Frame 023617/0647 →