Thyristor-based semiconductor memory device with back-gate bias

1. A semiconductor device, comprising:

a supporting substrate;

dielectric defining a layer on the supporting substrate;

semiconductor material disposed as a layer on the layer of dielectric; and

a thyristor of a memory cell defined in at least a portion of the semiconductor material layered over the dielectric;

a capacitor electrode disposed in insulated relationship over and capacitively coupled to a base region of the thyristor; and

a wordline coupled to the capacitor electrode;

wherein the supporting substrate on the side of the dielectric opposite the thyristor for the memory cell comprises semiconductor material defined at least in part by a portion against the dielectric, in which the portion against the dielectric has a density of dopants of at least 10 16 per cm 3 ; and

wherein the dielectric between the supporting substrate and the thyristor is sufficiently thin to enable back-gate biasing effects to a side of the semiconductor material of the thyristor that is opposite the capacitor electrode across the dielectric when a voltage bias of magnitude up to 5 volts is applied to the supporting substrate.

2. The device of claim 1 , in which the semiconductor material layered over the dielectric comprises a layer of silicon disposed on the dielectric as part of a silicon-on-insulator (SOI) wafer; and the entirety of the semiconductor material for the supporting substrate comprises said density of dopants.

3. The device of claim 1 , in which the dielectric is defined by a thickness sandwiched between the semiconductor material for the thyristor and that for the supporting substrate, the thickness of magnitude less than about 5000 angstroms.

4. The device of claim 3 , in which the device comprises a plurality of said memory cells of respective said thyristors for a memory array and a surface region of the supporting substrate, including that disposed against the dielectric of the given density of dopants, extends across an area per a planar view that is at least as great as an overlying area of the layered semiconductor material as defined by the memory array.

5. The device of claim 4 , further comprising a bias circuit to apply a voltage to the supporting substrate.

6. The device of claim 5 , in which the bias circuit is further operable to sense a temperature and adjust the magnitude of the voltage applied based on the temperature sensed.

7. The device of claim 6 , the bias circuit having a voltage versus temperature sensitivity sufficient to influence, when the device is operating, by way of the back-side biasing the gain of at least one component bipolar device of the thyristor of the memory cell dependent on the temperature sensed.

8. The device of claim 5 , further comprising:

at least one contact formed in the supporting substrate to receive the voltage of the bias circuit; and

in which the area of the surface region with said conductivity encompasses the at least one contact.

9. The device of claim 8 , in which peripheral regions of the supporting substrate outside the surface region beneath said memory array comprise density of dopants less than 10 16 per cm 3 .

10. A thyristor-based semiconductor memory device, comprising:

a supporting substrate comprising at least one of semiconductor material and conductor material;

dielectric layered on the supporting substrate;

a layer of silicon disposed on the dielectric;

the layer of silicon comprising doped regions of opposite sequential polarity that define a thyristor;

a wordline electrode disposed in insulated relationship over a base region of the thyristor;

a bias circuit electrically coupled to the supporting substrate to enable application of a given voltage to the supporting substrate when the memory device is operating;

wherein at least a portion of the supporting substrate is conductively and operatively configured to enable receipt and delivery of the given applied voltage to a location beneath the thyristor to impart a back-side bias electric field effect to the thyristor when the bias circuit applies the given voltage to the supporting substrate.

11. The memory device of claim 10 , in which the bias circuit is operably configured to, when the device is operating, sense a temperature and adjust the magnitude of the voltage bias applied to at least one of the electrode and the supporting substrate based on the temperature sensed.

12. The memory device of claim 11 , wherein the bias circuit is further operably configured to, when the device is operating, adjust the magnitude of the voltage applied to the supporting substrate with a voltage-versus-temperature dependency sufficient to compensate at least in part a given sensitivity in gain of the thyristor with respect to temperature.

13. The memory device of claim 12 , in which the bias circuit is electrically coupled to an ohmic contact formed in the supporting substrate; and

the interface region of the supporting substrate of the given dopant density comprises a lateral extent that encompasses the ohmic contact.