Poly-emitter type bipolar junction transistor, bipolar CMOS DMOS device, and manufacturing methods of poly-emitter type bipolar junction transistor and bipolar CMOS DMOS device
View Patent ↗A poly-emitter type bipolar transistor includes a buried layer formed over an upper portion of a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a collector area formed on the epitaxial layer and connected to the buried layer, a base area formed at a part of an upper portion of the epitaxial layer, and a poly-emitter area formed on a surface of the semiconductor substrate in the base area and including a polysilicon material. A BCD device includes a poly-emitter type bipolar transistor having a poly-emitter area including a polysilicon material and at least one of a CMOS and a DMOS formed on a single wafer together with the poly-emitter type bipolar transistor.
1. A method comprising:
forming buried layers at upper portions of a bipolar transistor region, a CMOS region and a DMOS region of a semiconductor substrate, respectively;
forming an epitaxial layer on the semiconductor substrate;
forming a collector area connected to the buried layers on the epitaxial layer of the bipolar transistor region;
forming an isolation layer that defines a base area and an emitter area;
forming a well area on the epitaxial layer of the CMOS region and the DMOS region;
forming the base area below the isolation layer in the semiconductor substrate of the bipolar transistor region, and forming the base electrode at an upper portion of the base area;
forming gates at the CMOS region and the DMOS region of the semiconductor substrate; and
forming a poly-emitter area at an upper portion of the base area, which is spaced apart from the base electrode by the isolation layer, in the bipolar transistor region.
2. The method of claim 1 , wherein the poly-emitter area is formed simultaneously with the gates of the CMOS and the DMOS through a single process.
3. The method of claim 1 , wherein a heavily doped well area is formed in the CMOS region and the DMOS region when the collector area is formed.
4. The method of claim 1 , wherein the forming of the well area on the epitaxial layer of the CMOS region and the DMOS region comprises:
forming at least one of a P-type well area and an N-type well area of the CMOS; and
forming a P-type body of the DMOS.
5. The method of claim 1 , wherein the forming of the gates and the poly-emitter area comprises:
forming an insulating layer on the epitaxial layer including the gates and the isolation layer;
forming a gate insulating layer of the CMOS and the DMOS by patterning the insulating layer, and removing the insulating layer from the epitaxial layer including the bipolar transistor region;
forming a polysilicon layer on the epitaxial layer including the gate insulating layer; and
forming gates on the gate insulating layer of the CMOS and DMOS by patterning the polysilicon layer and forming the poly-emitter on the emitter area defined by the isolation layer.
6. The method of claim 1 , wherein at least one of a logic circuit, a high-voltage MOS, an intermediate-voltage MOS, a low-voltage MOS, a drain extended MOS, a lateral double diffused MOS, a resistor, a capacitor, and a diode is integrated in a single wafer together with the bipolar transistor.
7. The method of claim 1 , including, after the gates and the poly-emitter are formed:
forming lightly doped drain areas at both sides of the gates of the CMOS and the DMOS;
forming a spacer; and
forming source/drain areas in the CMOS region, forming a P-type ion implantation area and a first N-type ion implantation area in the P-type body, and forming a second N-type ion implantation area in the DMOS region which is spaced apart from the P-type body by the isolation layer.
8. The method of claim 7 , including forming an insulating layer having at least one stack structure, a contact plug, and a metal interconnection after the source/drain areas and the ion implantation areas are formed.