Semiconductor process
View Patent ↗A semiconductor manufacturing process is provided. First, a substrate is provided, wherein a patterned conductive layer, a dielectric layer and a patterned metal hard mask layer are sequentially formed thereon. Thereafter, a portion of the dielectric layer is removed to form a damascene opening exposing the patterned conductive layer. Afterwards, the dielectric layer is heated to above 200° C. Thereafter, a plasma treatment process is performed on the damascene opening, wherein the gases used to generate the plasma include hydrogen gas and inert gas. Afterwards, a conductive layer is formed in the damascene opening to fill therein.
1. A semiconductor manufacturing process, comprising:
providing a substrate having a patterned conductive layer, a first dielectric layer and a patterned metal hard mask layer sequentially formed thereon;
removing a portion of the first dielectric layer to form a damascene opening exposing a portion of the patterned conductive layer;
performing a heating process for heating up the first dielectric layer to a temperature no less than 200° C.;
performing a plasma treatment process on the damascene opening, wherein a plasma used in the plasma treatment process is generated by a mixture gas including hydrogen and inert gas, wherein the damascene opening is formed with a first critical dimension before the plasma treatment process is performed and the damascene opening has a second critical dimension larger than the first critical dimension after the plasma treatment process is performed; and
forming a conductive layer in the damascene opening to fill the damascene opening.
2. The semiconductor manufacturing process of claim 1 , wherein the damascene opening is a dual damascene.
3. The semiconductor manufacturing process of claim 1 , wherein the molecule size of the inert gas is similar to the molecule size of the hydrogen.
4. The semiconductor manufacturing process of claim 1 , wherein the inert gas is helium.
5. The semiconductor manufacturing process of claim 1 , wherein the heating process is performed to heat up the first dielectric layer to the temperature of about 200° C.˜350° C.
6. The semiconductor manufacturing process of claim 1 , wherein, in the plasma treatment process, the power source of the plasma is a microwave power source.
7. The semiconductor manufacturing process of claim 1 , wherein a second dielectric layer is located between the first dielectric layer and the patterned metal hard mask layer.
8. The semiconductor manufacturing process of claim 1 , wherein a liner layer is located between the patterned conductive layer and the first dielectric layer.
9. The semiconductor manufacturing process of claim 8 , wherein the step of removing the portion of the first dielectric layer further comprises removing a portion of the liner layer.
10. The semiconductor manufacturing process of claim 1 , wherein a ratio of the hydrogen to the inert gas in the mixture gas is about 1:25˜1:10.
11. The semiconductor manufacturing process of claim 1 , wherein a gas flow of the mixture gas is about 5000 sccm˜10000 sccm.
12. The semiconductor manufacturing process of claim 1 , wherein a power of the plasma treatment process is about 1000˜2000 W.
13. The semiconductor manufacturing process of claim 1 , wherein a pressure of the plasma treatment process is about 500 mTorr˜1 Torr.
14. The semiconductor manufacturing process of claim 1 , wherein the method for removing the portion of the first dielectric layer includes dry etching process.
15. The semiconductor manufacturing process of claim 14 , wherein the method for removing the portion of the first dielectric layer is performed with the use of a fluorine-containing gas as an etching gas.
16. The semiconductor manufacturing process of claim 1 , before the heating process is performed, further comprising performing a cleaning process on the damascene opening.
17. The semiconductor manufacturing process of claim 16 , wherein the cleaning process is performed with the use of a cleaning solution containing hydrofluoric acid.
18. The semiconductor manufacturing process of claim 17 , wherein the cleaning solution comprises hydrofluoric acid of about 25˜1000 ppm, sulfuric acid of about 3˜10 wt % and water.
19. The semiconductor manufacturing process of claim 16 , after the cleaning process is performed and before the heating process is performed, further comprising performing a backside clean process.
20. The semiconductor manufacturing process of claim 1 , before the heating process is performed, further comprising performing a backside clean process.
21. The semiconductor manufacturing process of claim 1 , after the plasma treatment process is performed, further comprising performing a backside clean process.