Semiconductor device having stacked InGaP and GaAs layers, and method of making same
View Patent ↗It is desired for semiconductor devices to reduce leakage currents. In a semiconductor device having a stacked structure including a GaAs layer and an InGaP layer, p-type impurity is doped to the GaAs layer. Consequently, the conduction band of the GaAs is raised to higher than the Fermi level. As a result, electron accumulation is suppressed and the gate leakage current can be reduced.
1. A semiconductor device comprising:
a channel layer configured to flow a current;
a gate electrode formed to control the current; and
a two-layer structure in which an InGaP layer and a p-type GaAs layer being doped to be a p-type are in contact with one another, said two-layer structure being arranged on a same side of the channel layer as the gate electrode such that the p-type GaAs layer is between the channel layer and the InGaP layer.
2. The semiconductor device according to claim 1 , wherein the two-layer structure is arranged between the channel layer and the gate electrode.
3. The semiconductor device according to claim 1 , wherein the gate electrode extends into a recess formed in a part of the two-layer structure.
4. A semiconductor device in which plural kinds of semiconductor devices are stacked on a single substrate,
wherein a first kind semiconductor device among the plural kinds of semiconductor devices is the semiconductor device according to claim 1 and the two-layer structure is formed between the channel layer and the gate electrode, and
a second kind semiconductor device among the plural kinds of semiconductor devices is a semiconductor device having another gate electrode extending into a recess formed in a part of the two-layer structure.
5. The semiconductor device according to claim 4 , wherein the first kind semiconductor device is a depletion type field effect transistor, and
the second kind semiconductor device is an enhancement type field effect transistor.
6. The semiconductor device according to claim 1 , wherein the InGaP layer is an order type.
7. The semiconductor device according to claim 1 , wherein the InGaP layer is a disorder type.
8. The semiconductor device according to claim 1 , wherein the p-type GaAs layer is p-type doped evenly.
9. The semiconductor device according to claim 1 , wherein the p-type GaAs layer is p-type delta doped.
10. The semiconductor device according to claim 4 , wherein at least one of the gate electrode and the other gate electrode is a p-type semiconductor gate electrode made of a p-type semiconductor.
11. The semiconductor device according to claim 10 , wherein the p-type semiconductor electrode is a p-type GaAs gate electrode being a p-type doped GaAs layer.
12. The semiconductor device according to claim 4 , wherein at least one of the gate electrode and the other electrode is metal.
13. The semiconductor device according to claim 1 , wherein the channel layer is an undoped InGaAs layer, and
the semiconductor device further comprises:
an n-type doped AlGaAs layer on one or both sides of the channel layer and configured to be an electron supply layer.
14. The semiconductor device according to claim 13 , further comprising:
an undoped AlGaAs layer on a channel layer side of the p-type GaAs layer.
15. The semiconductor device according to claim 1 , wherein the channel layer is an n-type doped GaAs layer.
16. The semiconductor device according to claim 1 , wherein the channel layer is an n-type doped InGaAs layer, and
the semiconductor device further comprises:
an n-type doped AlGaAs layer on one or both sides of the channel layer and configured to be an electron supply layer.
17. The semiconductor device according to claim 1 , wherein the semiconductor device is a diode whose anode is the gate electrode.
18. The semiconductor device according to claim 1 , wherein a conduction band of the p-type doped GaAs layer is higher than the Fermi level such that electron accumulation in the p-type doped GaAs layer is suppressed.