Differential output circuit

1. A differential output circuit comprising:

a first output driving circuit that includes a first PMOS transistor and a first NMOS transistor connected in series to each other;

a second output driving circuit that includes a second PMOS transistor and a second NMOS transistor connected in series to each other; and

a control circuit,

wherein, when a control signal has a first value, the control circuit selectively turns on one of the first and second PMOS transistors and selectively turns on one of the first and second NMOS transistors, thereby controlling the first and second output driving circuits to output a first pair of differential signals, and

when the control signal has a second value, the control circuit supplies no current to the first and second PMOS transistors and selectively turns on one of the first and second NMOS transistors, thereby controlling the first and second output driving circuits to output a second pair of differential signals.

2. The differential output circuit according to claim 1 , further comprising:

a first current source circuit that is connected in series to the first and second output driving circuits,

wherein the amount of current flowing through the first current source circuit varies depending on the control signal.

3. The differential output circuit according to claim 2 ,

wherein, when the control signal has the first value, the first pair of differential signals are differentially output from the first and second output driving circuits according to an LVDS standard, and

when the control signal has the second value, the second pair of differential signals are differentially output according to a CML standard.

4. The differential output circuit according to claim 2 ,

wherein the amount of current flowing through the first current source circuit varies depending on a selection signal in addition to the control signal.

5. The differential output circuit according to claim 4 ,

wherein, when the control signal has the first value, the first pair of differential signals are differentially output from the first and second output driving circuits on the basis of the value of the selection signal, according to at least one of a subLVDS standard, an RSDS standard, and a mini-LVDS standard.

6. The differential output circuit according to claim 1 , further comprising:

a second current source circuit that is connected in series to the first and second output driving circuits;

a circuit that detects a center voltage between the pair of differential signals output from the first and second output driving circuits; and

a feedback circuit that changes the amount of current flowing through the second current source circuit according to a difference between the center voltage and a predetermined reference voltage.

7. The differential output circuit according to claim 6 ,

wherein the value of the reference voltage is changed to set the center voltage to a different value.

8. The differential output circuit according to claim 2 , further comprising:

a comparison circuit that compares a center voltage between the pair of differential signals output from the first and second output driving circuits with a predetermined threshold voltage, and changes the value of the control signal according to the comparison result.

9. The differential output circuit according to claim 6 ,

wherein the first current source circuit is connected in series to a power supply voltage side of each of the first and second output driving circuits, and

the second current source circuit is connected in series to a ground voltage side of each of the first and second output driving circuits.

10. The differential output circuit according to claim 6 ,

wherein the first current source circuit is connected in series to a ground voltage side of each of the first and second output driving circuits, and

the second current source circuit is connected in series to a power supply voltage side of each of the first and second output driving circuits.