IP Library Granted Patent US 7,833,857
Granted Patent B2
US 7,833,857 · App. 12/552,091 · Granted Nov 16, 2010

ESD protecting circuit and manufacturing method thereof

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Quick Facts
Patent No.
US 7,833,857
App. No.
12/552,091
Granted
Nov 16, 2010
Kind
B2
Abstract

An ESD protecting circuit and a manufacturing method thereof are provided. The ESD protecting circuit includes a device isolation layer, first and second high-concentration impurity regions, a third high-concentration impurity region of a complementary type, first and second conductive wells, and a fourth conductive impurity region. The ESD protecting circuit is configured as a field transistor without a gate electrode, and the high breakdown voltage characteristics of the field transistor are lowered by implanting impurity ions, providing an ESD protecting circuit with a low breakdown voltage and low leakage current. Because the leakage current is reduced, the ESD protecting circuit can be used for an analog I/O device that is sensitive to current fluxes. Also, an N-type well may protect a junction of the field transistor.

Claims (22)

1. A method of manufacturing an ESD protecting circuit, the method comprising:

forming a device isolation layer in a field region of a semiconductor substrate having a first conductivity type;

forming a first well and a second well in the semiconductor substrate;

forming a first high-concentration impurity region in the first and second wells and a second high-concentration impurity region in the first well, the first and second high-concentration impurity regions having a second conductivity type;

forming a third high-concentration impurity region in the first well on one side of the second high-concentration impurity region, the third high-concentration impurity region having the first conductivity type; and

forming a fourth impurity region below the first high-concentration impurity region at a boundary between the first and second wells, the fourth impurity region having the second conductivity type,

wherein the first well is in contact with and below the second and third high-concentration impurity region.

2. The method according to claim 1 , further comprising:

forming a silicide layer on surfaces of the first, second and third high-concentration impurity regions;

forming an insulating layer on the substrate;

forming plugs to the silicide layer on each of the first, second and third high-concentration impurity regions; and

forming a plurality of metal lines in contact with the plugs.

3. The method according to claim 1 , wherein forming the first and second high-concentration impurity regions comprises implanting N-type impurity ions in a dose sufficient to result in a concentration of 10 15 atoms/cm 2 or more, using an ion implanting energy of 50 KeV or less.

4. The method according to claim 1 , wherein forming the third high-concentration impurity region comprised implanting P-type impurity ions in a dose sufficient to result in a concentration of 10 15 atoms/cm 2 or more, using an ion implanting energy of 20 KeV or less.

5. The method according to claim 1 , wherein forming the fourth impurity region comprises implanting P-type impurity ions in a dose sufficient to result in a concentration of 3×10 13 to 7×10 13 atoms/cm 2 .

6. The method according to claim 5 , wherein the P-type impurity ions include B (boron).

7. The method according to claim 5 , wherein forming the fourth impurity region further comprises implanting P-type impurity ions at energy of 60 to 100 KeV.

8. The method according to claim 1 , further comprising forming first and second LDD regions before forming the first and second high-concentration impurity regions and the third high-concentration impurity region.

9. The method according to claim 1 , wherein the fourth impurity region is configured to reduce a breakdown voltage of the ESD protecting circuit.

10. The method according to claim 2 , wherein forming the insulating layer comprises blanket-depositing the insulating layer on an entire surface of the substrate.

11. The method according to claim 1 , wherein the first well is below a first portion of the first high-concentration impurity region.

12. The method according to claim 1 , wherein the second well is in contact with and below the second portion of the first high-concentration impurity region.

Assignments (2)
CHANGE OF NAME Recorded Nov 30, 2017
From: DONGBU HITEK CO., LTD.
To: DB HITEK CO., LTD
Reel/Frame 044555/0913 →
MERGER AND CHANGE OF NAME Recorded Nov 29, 2017
From: DONGBU ELECTRONICS CO., LTD.; DONGBU HITEK CO., LTD.
To: DONGBU HITEK CO., LTD.
Reel/Frame 044533/0523 →