Semiconductor chip with contoured solder structure opening

1. A method of manufacturing, comprising:

forming a first dielectric layer over a first conductor structure of a semiconductor chip; and

forming a first opening in the first dielectric layer to expose at least a portion of the first conductor structure, the first opening defining an interior wall that includes plural protrusions.

2. The method of claim 1 , comprising forming the first dielectric layer on a second dielectric layer that includes a second opening such that the first opening projects through the second opening.

3. The method of claim 1 , comprising coupling a solder structure to the first conductor structure such that a portion of the solder structure is positioned in the first opening.

4. The method of claim 3 , comprising coupling the solder structure to a circuit board.

5. The method of claim 4 , wherein the coupling of the solder structure comprises forming a second conductor structure on the first conductor structure and coupling the solder structure to the second conductor structure.

6. The method of claim 1 , wherein the first conductor structure comprises a dummy pad.

7. The method of claim 1 , wherein the forming of the first opening is performed by executing instructions stored in a computer readable medium.

8. A method of manufacturing, comprising:

coupling a solder structure to a first conductor structure of a semiconductor chip, the semiconductor chip including a first dielectric layer positioned over the first conductor structure and a first opening in the first dielectric layer that exposes at least a portion of the first conductor structure and defines an interior wall that includes plural protrusions; and

whereby the solder structure is coupled to the first conductor structure such that a portion of the solder structure is positioned in the first opening.

9. A method of coupling a semiconductor chip to a circuit board, comprising:

placing a portion of a first solder structure in a first opening in a first dielectric layer of the semiconductor chip, the first opening leading to at least a portion of a first conductor structure of the semiconductor chip and defining an interior wall that includes plural protrusions; and

coupling the first solder structure to the circuit board.

10. The method of claim 9 , wherein the coupling the first solder structure comprises coupling a second solder structure to the circuit board and thereafter coupling the first solder structure to the second solder structure.

11. The method of claim 9 , wherein the circuit board comprises a semiconductor chip package substrate.

12. The method of claim 9 , wherein first conductor comprises an input/output pad.

13. The method of claim 9 , wherein the first conductor comprises a dummy pad.

14. An apparatus, comprising:

a semiconductor chip including a first conductor structure and a first dielectric layer on the first conductor structure, the first dielectric layer including a first opening to the first conductor structure defining an interior wall of the first dielectric layer that includes plural protrusions; and

a solder structure coupled to the first conductor structure such that a portion of the solder structure is positioned in the first opening.

15. The apparatus of claim 14 , comprising a second dielectric layer beneath the first dielectric layer that includes a second opening through which the first opening projects.

16. The apparatus of claim 14 , comprising a circuit board coupled to the solder structure.

17. The apparatus of claim 14 , comprising a second conductor structure on the first conductor structure and coupled to the solder structure.

18. The apparatus of claim 14 , wherein the first dielectric layer comprises polyimide.

19. The apparatus of claim 14 , wherein the first conductor structure comprises an input/output pad.

20. The apparatus of claim 14 , wherein the first conductor structure comprises a dummy pad.