IP Library Granted Patent US 8,237,211
Granted Patent B2
US 8,237,211 · App. 12/556,242 · Granted Aug 7, 2012

Non-volatile semiconductor storage device and method of manufacturing the same

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,237,211
App. No.
12/556,242
Granted
Aug 7, 2012
Kind
B2
Abstract

A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.

Claims (48)

1. A non-volatile semiconductor storage device comprising:

a memory string including a plurality of electrically rewritable memory cells connected in series; and

a protruding layer formed to protrude upward with respect to a substrate,

the memory string comprising:

a plurality of first conductive layers laminated on the substrate and functioning as control electrodes of the memory cells;

a first semiconductor layer formed to penetrate the plurality of first conductive layers and functioning as a body of each of the memory cells; and

an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges to retain data of the memory cells,

each of the plurality of first conductive layers comprising:

a bottom portion extending in parallel to the substrate; and

a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion,

the protruding layer having a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.

2. The non-volatile semiconductor storage device according to claim 1 , wherein

the protruding layer is formed in a trapezoid shape; and

the side portion is formed to extend upward at a predetermined inclination angle to the substrate along the protruding layer.

3. The non-volatile semiconductor storage device according to claim 1 , wherein

the plurality of first conductive layers are formed to surround the protruding layer.

4. The non-volatile semiconductor storage device according to claim 1 , wherein

the protruding layers are formed in a stepwise manner in relation to each other so that a higher layer has a larger width in the first direction than a lower one.

5. The non-volatile semiconductor storage device according to claim 1 , wherein

the plurality of first conductive layers are configured to contain metal.

6. The non-volatile semiconductor storage device according to claim 1 , wherein

the protruding layers are formed at a predetermined pitch in the first direction and a second direction orthogonal to the first direction.

7. The non-volatile semiconductor storage device according to claim 1 , wherein

the protruding layer is formed in a rectangular shape as viewed from above.

8. The non-volatile semiconductor storage device according to claim 1 , wherein

the plurality of first conductive layers are formed in concave shapes with upward apertures.

9. The non-volatile semiconductor storage device according to claim 1 , further comprising:

a first selection transistor connected to one end of the memory string,

wherein the first selection transistor comprises:

a second conductive layer formed below a bottommost one of the first conductive layers and functioning as a control electrode of the first selection transistor;

a second semiconductor layer formed to penetrate the second conductive layer and in contact with the bottom surface of the first semiconductor layer, the second semiconductor layer functioning as a body of the first selection transistor; and

a first gate insulation layer formed between the second conductive layer and the second semiconductor layer.

10. The non-volatile semiconductor storage device according to claim 1 , further comprising:

a second selection transistor connected to the other end of the memory string,

wherein the second selection transistor comprises:

a third conductive layer formed above a topmost one of the first conductive layers and functioning as a control electrode of the second selection transistor;

a third semiconductor layer formed to penetrate the third conductive layer and in contact with a top surface of the first semiconductor layer, the third semiconductor layer functioning as a body of the second selection transistor; and

a second gate insulation layer formed between the third conductive layer and the third semiconductor layer.

11. The non-volatile semiconductor storage device according to claim 1 , wherein

the protruding layer comprises:

a columnar layer formed in a columnar shape, the columnar layer including silicon oxide; and

a sidewall layer formed on a sidewall of the columnar layer, the sidewall layer including silicon nitride.

12. The non-volatile semiconductor storage device according to claim 1 , further comprising:

an interlayer insulation layer formed above the first conductive layers; and

a first contact plug layer formed to penetrate the interlayer insulation layer and to reach a top surface of the side portion of each of the first conductive layers.

13. The non-volatile semiconductor storage device according to claim 9 , further comprising:

an interlayer insulation layer formed above the protruding layer; and

a second contact plug layer formed to penetrate the interlayer insulation layer and the protruding layer and to reach a top surface of the second conductive layer.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 25, 2009
From: FUKUZUMI, YOSHIAKI; KATSUMATA, RYOTA; KITO, MASARU; TANAKA, HIROYASU; KIDOH, MASARU; KOMORI, YOSUKE; ISHIDUKI, MEGUMI; NITAYAMA, AKIHIRO; AOCHI, HIDEAKI; ITO, HITOSHI; MATSUOKA, YASUYUKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 023568/0809 →
Priority Claims (1)
JP 2008-269804 · Oct 20, 2008 · national
Continuity (1)
Related Publication 20100096682A1 · Apr 22, 2010