IP Library Granted Patent US 8,060,333
Granted Patent B2
US 8,060,333 · App. 12/557,443 · Granted Nov 15, 2011

Test apparatus and test method

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Quick Facts
Patent No.
US 8,060,333
App. No.
12/557,443
Granted
Nov 15, 2011
Kind
B2
Abstract

Provided is a test apparatus that tests a device under test, including a pattern list storage section that stores a plurality of pattern lists that each designate, in a prescribed order, the test patterns to be output by the device under test, and a pattern list processing section that (i) sequentially outputs the test patterns by sequentially executing the pattern lists according to test results of the device under test and, (ii) when transitioning from a current pattern list to a subsequent pattern list, repeatedly outputs a prescribed idle pattern until execution of the subsequent pattern list is begun.

Claims (32)

1. A test apparatus that tests a device under test, comprising:

a pattern list storage section that stores a plurality of pattern lists that each designate, in a prescribed order, the test patterns to be output by the device under test; and

a pattern list processing section that (i) sequentially outputs the test patterns by sequentially executing the pattern lists according to test results of the device under test and, (ii) when transitioning from a current pattern list to a subsequent pattern list, repeatedly outputs a prescribed idle pattern until execution of the subsequent pattern list is begun, wherein

each pattern list includes:

a wait instruction for repeatedly outputting a prescribed idle pattern until a prescribed condition is fulfilled; and

a jump instruction for designating the subsequent pattern list to be executed after the current pattern list, after the wait instruction has ended, and

the test apparatus further includes a control section that designates a jump destination indicated by the jump instruction included in each pattern list, after execution of the pattern list has begun.

2. The test apparatus according to claim 1 , wherein

the pattern list storage section stores the pattern lists that each have the wait instruction and the jump instruction at the end thereof.

3. The test apparatus according to claim 2 , wherein

when the test result of the device under test fulfills the prescribed condition, the pattern list processing section ends execution of the wait instruction and executes the jump instruction, and

the control section designates, as the jump destination of the jump instruction, a pattern list that corresponds to the test result of the device under test.

4. The test apparatus according to claim 3 , wherein

the control section designates the jump destination of a jump instruction while the pattern list processing section is repeatedly executing the corresponding wait instruction.

5. The test apparatus according to claim 4 , further comprising

a register that stores addresses of jump destinations of jump instructions, wherein the control section writes the addresses in the register.

6. The test apparatus according to claim 2 , wherein

the pattern list storage section stores pattern lists in which an instruction code including a wait instruction and a jump instruction is associated with operands that designate test patterns, the pattern lists designating an order of output of the test patterns by executing the instruction code, and

the pattern list processing section sequentially outputs the test patterns by performing, in advance, a look-ahead process for (i) the instruction code to be performed prior to the instruction code being currently performed and (ii) the corresponding test pattern, and stopping the look-ahead process when the wait instruction is detected by the look-ahead process.

7. The test apparatus according to claim 6 , wherein

after the jump instruction is executed, the pattern list processing section resumes the look-ahead process.

8. The test apparatus according to claim 2 , wherein

the pattern list processing section repeatedly outputs a prescribed number of the test patterns output immediately before the wait instruction, as the idle pattern.

9. The test apparatus according to claim 8 , wherein

the wait instruction changes the prescribed number of test patterns according to a designated value.

10. A method for testing a device under test, comprising:

storing a plurality of pattern lists that each designate, in a prescribed order, the test patterns to be output by the device under test; and

(i) sequentially outputting the test patterns by sequentially executing the pattern lists according to test results of the device under test and, (ii) when transitioning from a current pattern list to a subsequent pattern list, repeatedly outputting a prescribed idle pattern until execution of the subsequent pattern list is begun, wherein

each pattern list includes:

a wait instruction for repeatedly outputting a prescribed idle pattern until a prescribed condition is fulfilled; and

a jump instruction for designating the subsequent pattern list to be executed after the current pattern list, after the wait instruction has ended, and

the method further comprises designating a jump destination indicated by the jump instruction included in each pattern list, after execution of the pattern list has begun.

Assignments (2)
CHANGE OF ADDRESS Recorded Dec 18, 2018
From: ADVANTEST CORPORATION
To: ADVANTEST CORPORATION
Reel/Frame 047987/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 24, 2009
From: ISHIKAWA, SHINICHI
To: ADVANTEST CORPORATION
Reel/Frame 023566/0740 →