Test apparatus synchronous module and synchronous method

1. A test apparatus that tests a device under test, comprising:

a processor;

a memory in communication with the processor;

a plurality of test modules that test the device under test;

a synchronization module in communication with the processor and connected to each of the plurality of test modules, and that synchronizes the plurality of test modules; and

a test control section that is connected to the plurality of test modules and the synchronization module, and that controls the test modules and the synchronization module, wherein

the synchronization module includes:

a receiving section in communication with the memory that receives, from each of the plurality of test modules, a ready signal indicating that the test module is in a ready state;

an aggregating section in communication with the memory that generates an aggregate ready signal indicating that the plurality of test modules are in the ready state, on a condition that ready signals have been received from all of the plurality of test modules; and

a transmitting section in communication with the memory that transmits, to each of the plurality of test modules, a common synchronization signal ordering test initiation, in response to the generation of the aggregate ready signal, such that the test modules are commonly synchronized.

2. The test apparatus according to claim 1 , wherein

the transmitting section transmits the synchronization signal ordering writing to a control register in each of the plurality of test modules.

3. The test apparatus according to claim 2 , wherein

the transmitting section transmits, to at least one of the test modules, a read request signal ordering reading of a state register that indicates the state of the test module, and

the receiving section receives, from the at least one test module, the ready signal as a read response to the read request.

4. The test apparatus according to claim 1 , wherein

the synchronization module includes a synchronization control section, which executes a synchronization program stored in the memory corresponding to the aggregate ready signal to cause the transmitting section to transmit, to the plurality of test modules, the common synchronization signal ordering an operation corresponding to a result of the execution.

5. The test apparatus according to claim 4 , wherein

the aggregating section interrupts the synchronization control section in response to the generation of a predetermined aggregate ready signal, and

upon receiving the interrupt, the synchronization control section executes the synchronization program corresponding to the aggregate ready signal that caused the interrupt.

6. A test apparatus that tests a device under test, comprising:

a processor;

a memory in communication with the processor;

a plurality of test modules that test the device under test;

a synchronization module in communication with the processor and connected to each of the plurality of test modules, and that synchronizes the plurality of test modules; and

a test control section that is connected to the plurality of test modules and the synchronization module, and that controls the test modules and the synchronization module, wherein

the synchronization modules includes:

a receiving section in communication with the memory that receives, from at least one of the plurality of test modules, a fail signal indicating that a failure has occurred in the test by the test module;

an aggregating section in communication with the memory that generates an aggregate fail signal indicating that a test has failed, on a condition that a fail signal is received from at least one of the plurality of test modules; and

a transmitting section in communication with the memory that transmits, to each of the plurality of test modules, a common synchronization signal ordering stoppage of the test, in response to the generation of the aggregate fail signal, such that the test modules are commonly synchronized.

7. The test apparatus according to claim 6 , wherein

the transmitting section transmits the synchronization signal ordering writing to a control register in each of the plurality of test modules.

8. The test apparatus according to claim 7 , wherein

the transmitting section transmits, to at least one of the test modules, a read request signal ordering reading of a state register that indicates the state of the test module, and

the receiving section receives, from the at least one test module, the fail signal as a read response to the read request.

9. The test apparatus according to claim 6 , wherein

the synchronization module includes a synchronization control section, which executes a synchronization program stored in the memory corresponding to the aggregate fail signal to cause the transmitting section to transmit, to the plurality of test modules, the common synchronization signal ordering an operation corresponding to a result of the execution.

10. The test apparatus according to claim 9 , wherein

the aggregating section interrupts the synchronization control section in response to the generation of a predetermined aggregate fail signal, and

upon receiving the interrupt, the synchronization control section executes the synchronization program corresponding to the aggregate fail signal that caused the interrupt.

11. A synchronization module for use with a test apparatus that tests a device under test, the synchronization module comprising:

a memory;

a receiving section that receives, from each of the plurality of test modules, a ready signal indicating that the test module is in a ready state;

an aggregating section that generates an aggregate ready signal indicating that the plurality of test modules are in the ready state, on a condition that ready signals have been received from all of the plurality of test modules; and

a transmitting section that transmits, to each of the plurality of test modules, a common synchronization signal ordering test initiation, in response to the generation of the aggregate ready signal, such that the test modules are commonly synchronized.

12. A synchronization method for testing a device under test with a test apparatus that includes (i) a plurality of test modules that test the device under test, (ii) a synchronization module that is connected to each of the plurality of test modules, and that synchronizes the plurality of test modules, and (iii) a test control section that is connected to the plurality of test modules and the synchronization module, and that controls the test modules and the synchronization module, the synchronization method comprising:

the synchronization module receiving, from at least one of the plurality of test modules, a ready signal indicating that the test module is in a ready state,

the synchronization module generating an aggregate ready signal indicating that the plurality of test modules are in the ready state, on a condition that ready signals have been received from all of the plurality of test modules, and

the synchronization module transmitting, to each of the plurality of test modules, a common synchronization signal ordering test initiation, in response to the generation of the aggregate ready signal, such that the test modules are commonly synchronized.

13. The synchronization method according to claim 12 , wherein

the synchronization module transmits the synchronization signal ordering writing to a control register in each of the plurality of test modules.

14. The synchronization method according to claim 13 , wherein

the synchronization module transmits, to at least one of the test modules, a read request signal ordering reading of a state register that indicates the state of the test module, and

the synchronization module receives, from the at least one test module, the ready signal as a read response to the read request.

15. The synchronization method according to claim 12 , wherein

the synchronization module executes a synchronization program corresponding to the aggregate ready signal to cause the synchronization module to transmit, to the plurality of test modules, the common synchronization signal ordering an operation corresponding to a result of the execution.

16. The synchronization method according to claim 15 , wherein

upon receiving an interrupt in response to the generation of a predetermined aggregate ready signal, the synchronization module executes the synchronization program corresponding to the aggregate ready signal that caused the interrupt.

17. A synchronization method for testing a device under test with a test apparatus that includes (i) a plurality of test modules that test the device under test, (ii) a synchronization module that is connected to each of the plurality of test modules, and that synchronizes the plurality of test modules, and (iii) a test control section that is connected to the plurality of test modules and the synchronization module, and that controls the test modules and the synchronization module, the synchronization method comprising:

the synchronization module receiving, from each of the plurality of test modules, a fail signal indicating that a failure has occurred in the test by the test module,

the synchronization module generating an aggregate fail signal indicating that a test has failed, on a condition that a fail signal is received from at least one of the plurality of test modules, and

the synchronization module transmitting, to each of the plurality of test modules, a common synchronization signal ordering stoppage of the test, in response to the generation of the aggregate fail signal, such that the test modules are commonly synchronized.

18. The synchronization method according to claim 17 , wherein

the synchronization module transmits the synchronization signal ordering writing to a control register in each of the plurality of test modules.

19. The synchronization method according to claim 18 , wherein

the synchronization module transmits, to at least one of the test modules, a read request signal ordering reading of a state register that indicates the state of the test module, and

the synchronization module receives, from the at least one test module, the fail signal as a read response to the read request.

20. The synchronization method according to claim 17 , wherein

the synchronization module executes a synchronization program corresponding to the aggregate fail signal to cause the synchronization module to transmit, to the plurality of test modules, the common synchronization signal ordering an operation corresponding to a result of the execution.

21. The synchronization method according to claim 20 , wherein

upon receiving an interrupt in response to the generation of a predetermined aggregate fail signal, the synchronization module executes the synchronization program corresponding to the aggregate fail signal that caused the interrupt.

22. A synchronization module for use with a test apparatus that tests a device under test, the synchronization module comprising:

a memory;

a receiving section that receives, from each of the plurality of test modules, a fail signal indicating that a failure has occurred in the test by the test module;

an aggregating section that generates an aggregate fail signal indicating that a test has failed, on a condition that a fail signal is received from at least one of the plurality of test modules; and

a transmitting section that transmits, to each of the plurality of test modules, a common synchronization signal ordering stoppage of the test, in response to the generation of the aggregate fail signal, such that the test modules are commonly synchronized.