Structures and Methods for Wafer Packages, and Probes
This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices. In some embodiments, such structures are shown to be useful for simultaneously testing multiple devices on a semiconductor wafer, or for assembling multiple substrates on to a wafer, to accomplish both testing and packaging of the dies on the wafer. In yet another embodiment of the invention, single or multilevel ceramic interconnect structures with thick film metal conductors, are fabricated right on the product wafer to facilitate economical testing and packaging of the dies on the wafer.
1 . A contactor comprising:
an insulating substrate having a top surface and a bottom surface;
a plurality of conductive top via extensions, the top via extensions protruded partially above the top surface with higher than 2×1 aspect ratio;
a plurality of conductive bottom via extensions, the bottom via extensions protruded partially above the bottom surface with higher than 2×1 aspect ratio;
one or more layers of interconnects located within the insulating substrate, each interconnect connecting a number of via extensions.
2 . A contactor as in claim 1 wherein the protruding via extensions are embedded partially in the insulating substrate.
3 . A contactor as in claim 1 further comprising:
a plurality of conductive vias, the vias totally embedded within the insulating substrate and connecting the interconnects between the layers.
4 . A contactor as in claim 1 wherein the number of via extensions is more than the number of bottom via extensions.
5 . A contactor as in claim 1 wherein the insulating substrate is a ceramic substrate.
6 . A contactor as in claim 1 wherein the via extension protrudes less than 1 mm from the top surface.
7 . A contactor as in claim 1 wherein the via extensions are having a uniform height.
8 . A contactor as in claim 1 wherein the via extensions are straight, staggered or having a cantilevel structure.
9 . A contactor as in claim 1 wherein the insulating substrate has a thermal coefficient similar to that of silicon.
10 . A contactor as in claim 1 wherein the insulating substrate comprising a composition of MgO, Al 2 O 3 , and SiO 2 .
11 . A contactor as in claim 1 wherein the via extensions are coated with a solder material, or presenting a solderable conductive surface.
12 . A contactor comprising:
an insulating substrate having a top surface;
a plurality of top conductive via extensions, the via extensions protruded partially above the top surface;
one or more layers of interconnects located within the insulating substrate, each interconnect connecting a number of via extensions;
a plurality of contact tips disposed on top of the via extensions, the contact tips having the planarity and the spacing accuracy of semiconductor processing,
wherein the contact tips bonded to the via extensions by soldering.
13 . A contactor as in claim 12 wherein the tips are fabricated separately on a semiconductor substrate before attaching to the via extensions.
14 . A contactor comprising:
an insulating substrate having a top surface;
a plurality of top conductive via extensions, the via extensions protruded partially above the top surface;
one or more layers of interconnects located within the insulating substrate, each interconnect connecting a number of via extensions,
wherein the via extensions comprise a constricted solder bridge to allow ease of rework.
15 . A contactor as in claim 14 wherein the via extensions comprise an insulating coating with opening on top.
16 . A contactor as in claim 14 wherein the via extensions have a portion of the side surface near the top surface of the insulating substrate protected from being soldered.
17 . A contactor as in claim 14 wherein the via extensions have a polyimide coating on a portion of the side surface near the top surface of the insulating substrate.
18 . A contactor as in claim 14 wherein the via extensions have the top surface solderable or coated with solder.
19 . A chip package comprising:
a contactor comprising
an insulating substrate having a top surface;
a plurality of conductive via extensions, the via extensions protruded partially above the top surface; and
one or more layers of interconnects located within the insulating substrate, each interconnect connecting a number of via extensions;
a semiconductor chip having a top surface with a plurality of interconnect bond pads,
wherein the via extensions bond to the bond pads by solder.
20 . A chip package as in claim 19 wherein the bonded area of the via extensions to the bond pads are constricted.
21 . A chip package as in claim 19 wherein only the top of the via extensions bond to the bond pads with a solder.
22 . A chip package as in claim 19 wherein the top and a portion of the sides of the via extensions bond to the bond pads with a solder.
23 . A chip package as in claim 19 wherein the contactor bonds to a plurality of semiconductor chips.
24 . A chip package as in claim 19 wherein the contactor bonds to semiconductor chips in a whole semiconductor wafer.