Schottky barrier CMOS device and method
A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.
1. An integrated circuit on a semiconductor substrate, the integrated circuit comprising:
at least one Schottky barrier NMOS device comprising:
a first metal type source extension and drain extension;
a second metal type source electrode and drain electrode, wherein the second metal type source electrode and drain electrode extend deeper into the semiconductor substrate than the first metal type source extension and drain extension;
a first channel region that extends between the first metal type source extension and drain extension;
a first type gate electrode; and
a sidewall spacer, wherein the first metal type source extension and drain extension extend at least partially below the sidewall spacer; and
at least one Schottky barrier PMOS device comprising:
a third metal type source extension and drain extension;
a fourth metal type source electrode and drain electrode, wherein the fourth metal type source electrode and drain electrode extend deeper into the semiconductor substrate than the third metal type source extension and drain extension;
a second channel region that extends between the third metal type source extension and drain extension;
a second type gate electrode; and
a sidewall spacer, wherein the third metal type source extension and drain extension extend at least partially below the sidewall spacer.
2. The circuit of claim 1 ,
wherein the second metal type source electrode forms a Schottky or Schottky-like contact with the semiconductor substrate at least in areas adjacent to the first channel region, and
wherein the fourth metal type source electrode forms a Schottky or Schottky-like contact with the semiconductor substrate at least in areas adjacent to the second channel region.
3. The circuit of claim 1 ,
wherein the second metal type source electrode forms a Schottky or Schottky-like contact with the semiconductor substrate at least in areas adjacent to the first channel region, and
wherein the fourth metal type drain electrode forms a Schottky or Schottky-like contact with the semiconductor substrate at least in areas adjacent to the second channel region.
4. The circuit of claim 1 ,
wherein the second metal type drain electrode forms a Schottky or Schottky-like contact with the semiconductor substrate at least in areas adjacent to the first channel region, and
wherein the fourth metal type source electrode forms a Schottky or Schottky-like contact with the semiconductor substrate at least in areas adjacent to the second channel region.
5. The circuit of claim 1 ,
wherein the second metal type drain electrode forms a Schottky or Schottky-like contact with the semiconductor substrate at least in areas adjacent to the first channel region, and
wherein the fourth metal type drain electrode forms a Schottky or Schottky-like contact with the semiconductor substrate at least in areas adjacent to the second channel region.
6. The circuit of claim 1 , wherein the first type gate electrode is on a thin insulator layer on the semiconductor substrate, and wherein the second type gate electrode is on the thin insulator layer on the semiconductor substrate.
7. The circuit of claim 1 , wherein the first type gate electrode is on a thin insulator layer on the semiconductor substrate, wherein the second type gate electrode is on the thin insulator layer on the semiconductor substrate, and wherein at least a portion of the thin insulator layer has a dielectric constant greater than 4.0.
8. The circuit of claim 1 , wherein the first type gate electrode is on a thin insulator layer on the semiconductor substrate, wherein the second type gate electrode is on the thin insulator layer on the semiconductor substrate, and wherein at least a portion of the thin insulator layer is formed from a member of a group consisting of metal oxides.
9. The circuit of claim 1 , wherein the semiconductor substrate is strained.
10. The circuit of claim 1 , wherein the first channel region is strained.
11. The circuit of claim 1 , wherein the second channel region is strained.
12. The circuit of claim 1 , wherein both the first and second channel regions are strained.
13. The circuit of claim 1 , wherein the first channel region has a first doping type and a first doping concentration profile, and wherein the second channel region has a second doping type and a second doping concentration profile.
14. The circuit of claim 1 ,
wherein the at least one Schottky barrier NMOS device further comprises a P-type well, and
wherein the at least one Schottky barrier PMOS device further comprises an N-type well, and
wherein at least the P-type well is not electrically contacted via ohmic contacts.
15. The circuit of claim 1 ,
wherein the at least one Schottky barrier NMOS device further comprises a P-type well, and
wherein the at least one Schottky barrier PMOS device further comprises an N-type well, and
wherein at least the N-type well is not electrically contacted via ohmic contacts.
16. The circuit of claim 1 ,
wherein the at least one Schottky barrier NMOS device further comprises a P-type well, and
wherein the at least one Schottky barrier PMOS device further comprises an N-type well, and
wherein both the P-type and N-type wells are not electrically contacted via ohmic contacts.
17. The circuit of claim 1 ,
wherein the second metal type and the fourth metal type are both Cobalt Silicide.
18. The circuit of claim 1 ,
wherein the second metal type and the fourth metal type are each members of the group consisting of mid-gap Silicides.
19. An integrated circuit on a semiconductor substrate, the integrated circuit comprising:
at least one Schottky barrier NMOS device comprising:
a first metal type source extension and drain extension;
a second metal type source electrode and drain electrode, wherein the second metal type source electrode and drain electrode extend deeper into the semiconductor substrate than the first metal type source extension and drain extension;
a first channel region that extends between the first metal type source extension and drain extension;
a first type gate electrode; and
a sidewall spacer, wherein the first metal type source extension and drain extension extend at least partially below the sidewall spacer; and
at least one Schottky barrier PMOS device comprising:
a third metal type source extension and drain extension;
a fourth metal type source electrode and drain electrode, wherein the fourth metal type source electrode and drain electrode extend deeper into the semiconductor substrate than the third metal type source extension and drain extension;
a second channel region that extends between the third metal type source extension and drain extension;
a second type gate electrode; and
a sidewall spacer, wherein the third metal type source extension and drain extension extend at least partially below the sidewall spacer, wherein the second metal type and the fourth metal type comprise a same metal type.
20. An integrated circuit on a semiconductor substrate, the integrated circuit comprising:
at least one Schottky barrier NMOS device comprising:
a first metal type source extension and drain extension;
a second metal type source electrode and drain electrode, wherein the second metal type source electrode and drain electrode extend deeper into the semiconductor substrate than the first metal type source extension and drain extension;
a first channel region that extends between the first metal type source extension and drain extension;
a first type gate electrode; and
a sidewall spacer, wherein the first metal type source extension and drain extension extend at least partially below the sidewall spacer; and
at least one Schottky barrier PMOS device comprising:
a third metal type source extension and drain extension;
a fourth metal type source electrode and drain electrode, wherein the fourth metal type source electrode and drain electrode extend deeper into the semiconductor substrate than the third metal type source extension and drain extension;
a second channel region that extends between the third metal type source extension and drain extension;
a second type gate electrode; and
a sidewall spacer, wherein the third metal type source extension and drain extension extend at least partially below the sidewall spacer,
wherein the second metal type and the fourth metal type comprise a same metal type, and
wherein the same metal type is formed from a member of the group consisting of mid-gap Silicides.