Semiconductor memory device
A semiconductor memory device includes: a semiconductor substrate; a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked, the stacked body being provided on the semiconductor substrate; a semiconductor layer provided inside a hole formed through the stacked body, the semiconductor layer extending in stacking direction of the conductive layers and the dielectric layers; and a charge storage layer provided between the conductive layers and the semiconductor layer. The stacked body in a memory cell array region including a plurality of memory strings is divided into a plurality of blocks by slits with an interlayer dielectric film buried therein, the memory string including as many memory cells series-connected in the stacking direction as the conductive layers, the memory cell including the conductive layer, the semiconductor layer, and the charge storage layer provided between the conductive layer and the semiconductor layer, and each of the block is surrounded by the slits formed in a closed pattern.
1. A semiconductor memory device comprising:
a semiconductor substrate;
a stacked body including a plurality of conductive layers and a plurality of dielectric layers alternately stacked, the stacked body being provided on the semiconductor substrate;
a semiconductor layer provided inside a hole formed through the stacked body, the semiconductor layer extending in stacking direction of the conductive layers and the dielectric layers; and
a charge storage layer provided between the conductive layers and the semiconductor layer,
the stacked body in a memory cell array region including a plurality of memory strings being divided into a plurality of blocks by slits with an interlayer dielectric film buried therein, the memory string including as many memory cells series-connected in the stacking direction as the conductive layers, each memory cell including the conductive layer, the semiconductor layer, and the charge storage layer provided between the conductive layer and the semiconductor layer, and each of the blocks being surrounded by the slits formed in a closed pattern in a planar view.
2. The device according to claim 1 , wherein the slits extend also in dividing direction of the plurality of blocks.
3. The device according to claim 1 , wherein the slits have a width narrowing from its opening end side toward its bottom.
4. The device according to claim 1 , wherein the memory cells have a charge trap structure.
5. The device according to claim 4 , wherein the charge storage layer is a silicon nitride film.
6. The device according to claim 1 , further comprising:
a first dielectric film provided between the conductive layer and the charge storage layer.
7. The device according to claim 1 , further comprising:
a second dielectric film provided between the charge storage layer and the semiconductor layer.
8. The device according to claim 1 , wherein the dielectric layer includes silicon oxide.
9. The device according to claim 1 , wherein the conductive layer is a silicon layer.
10. The device according to claim 1 , wherein the semiconductor layer is a silicon layer.
11. The device according to claim 1 , wherein the interlayer dielectric film includes silicon oxide.
12. The device according to claim 1 , wherein the plurality of conductive layers are formed into a staircase shape in an end portion of the memory cell array region.
13. The device according to claim 12 , wherein a dielectric film is provided on the staircase-shaped portion of the conductive layers.
14. The device according to claim 13 , wherein
a contact hole penetrating through the dielectric film and reaching the staircase-shaped portion of the conductive layers is formed in the dielectric film, and
a conductive material is provided in the contact hole.
15. The device according to claim 1 , wherein
a peripheral circuit region is formed around the memory cell array region, and
the stacked body with the plurality of conductive layers and the plurality of dielectric layers alternately stacked is provided also in the peripheral circuit region.
16. The device according to claim 15 , wherein
a sense amplifier configured to read data stored in the memory cell is provided in the peripheral circuit region, and
the stacked body around the sense amplifier is also provided with the slits formed in a closed pattern surrounding the sense amplifier.
17. The device according to claim 16 , wherein the slits separate the memory cell array region from the sense amplifier.
18. The device according to claim 15 , wherein
a row decoder configured to select the conductive layer in the memory cell array region is provided in the peripheral circuit region, and
the stacked body around the row decoder is also provided with the slits formed in a closed pattern surrounding the row decoder.
19. The device according to claim 18 , wherein the slits separate the memory cell array region from the row decoder.
20. The device according to claim 1 , wherein the slits are also formed immediately inside a dicing line for separating the semiconductor substrate into chips and surround the chip in a closed-loop pattern.