Semiconductor integrated circuit and method for controlling semiconductor integrated circuit
A semiconductor integrated circuit includes memories, a BIST circuit, and an analyzer. The BIST circuit includes a test controller performing the test and generating a memory selection signal selecting a memory to be tested, an address generator generating write and read addresses, a data generator generating write data and an expected output value, and a control signal generator generating a control signal. The analyzer includes a memory output selector selecting output data, a bit comparator comparing the output data with the expected output value, an error detection unit determining whether there is an error in the memory, a plurality of pass/fail flag registers capable of storing a pass/fail flag, a repair analyzer analyzing a memory error and generating a repair analysis result, a plurality of repair analysis result registers capable of storing the repair analysis result, and an output unit outputting the pass/fail flag and the repair analysis result.
1. A semiconductor integrated circuit comprising:
a plurality of memories configured to store data;
a built-in self-test circuit configured to perform a test for the plurality of memories, the built-in self-test circuit comprising:
a test controller configured to perform the test and generate a memory selection signal selecting a memory to be tested from the plurality of memories;
an address generator configured to generate write and read addresses;
a data generator configured to generate write data and an expected output value of the memory corresponding to the write data; and
a control signal generator configured to generate a control signal performing a write operation for the write data to the write address of the memory and a read operation for read address of the memory; and
an analyzer configured to analyze a test result of the built-in self-test circuit, the analyzer comprising:
a memory output selector configured to select output data of the plurality of memories based on the memory selection signal generated by the test controller;
a bit comparator configured to compare the output data selected by the memory output selector with the expected output value generated by the data generator bit by bit;
an error detection unit configured to determine whether there is an error in the memory based on a comparison result of the bit comparator;
a plurality of pass/fail flag registers corresponding to the plurality of memories and configured to store a pass/fail flag of the error detection unit;
a repair analyzer configured to analyze a memory error based on the comparison result of the bit comparator and generate a repair analysis result;
a plurality of repair analysis result registers corresponding to the plurality of memories and configured to store the repair analysis result generated by the repair analyzer; and
an output unit configured to output the pass/fail flag stored in the plurality of pass/fail flag registers and the repair analysis result stored in the plurality of repair analysis result registers.
2. The circuit of claim 1 , further comprising a capture register located between the error detection unit or the repair analyzer and the memory output selector, and configured to store the output data selected by the memory output selector.
3. The circuit of claim 2 , wherein
the plurality of memories comprises some memories having different bit widths from each other, and
the bit comparator masks a bit of the expected output value in such a manner that the bit width of the output data selected by the memory output selector is a maximum bit width of the plurality of memories when the output data is not the maximum bit width.
4. The circuit of claim 1 , wherein
the plurality of memories comprises some memories having different bit widths from each other, and
the bit comparator masks a bit of the expected output value in such a manner that the bit width of the output data selected by the memory output selector is a maximum bit width of the plurality of memories when the output data is not the maximum bit width.
5. The circuit of claim 1 , wherein
each pass/fail flag register stores the pass/fail flag for each memory instance, and
each repair analysis result register stores the repair analysis result for each memory instance.
6. The circuit of claim 1 , wherein the plurality of memories comprises a selector configured to select an input terminal for system or an input terminal for test.
7. A semiconductor integrated circuit comprising:
a plurality of memories configured to store data;
a built-in self-test circuit configured to perform a test for the plurality of memories, the built-in self-test circuit comprising:
a test controller configured to perform the test in such a manner that one test is synchronized with the other test and generate a memory selection signal selecting a memory to be tested from the plurality of memories;
an address generator configured to generate write and read addresses;
a data generator configured to generate write data and an expected output value of the memory corresponding to the write data; and
a control signal generator configured to generate a control signal performing a write operation for the write data to the write address of the memory and a read operation for read address of the memory; and
an analyzer configured to analyze a test result of the built-in self-test circuit, the analyzer comprising:
a memory output selector configured to select output data of the plurality of memories based on the memory selection signal generated by the test controller;
a bit comparator configured to compare the output data selected by the memory output selector with the expected output value generated by the data generator bit by bit;
an error detection unit configured to determine whether there is an error in the memory based on a comparison result of the bit comparator;
a pass/fail flag register configured to store a pass/fail flag of the error detection unit;
a repair analyzer configured to analyze a memory error based on the comparison result of the bit comparator and generate a repair analysis result;
a repair analysis result register configured to store the repair analysis result generated by the repair analyzer; and
an output unit configured to output the pass/fail flag stored in the pass/fail flag register and the repair analysis result stored in the repair analysis result register.
8. The circuit of claim 7 , wherein
the pass/fail flag register comprises a first and second pass/fail flag registers configured to store the pass/fail flag,
the repair analysis result register comprises a first and second repair analysis result registers configured to store the repair analysis result,
when the test for one memory instance is completed, in the pass/fail flag register, the pass/fail flag stored in the first pass/fail flag register is transferred to the second pass/fail flag register, and in the repair analysis result register, the repair analysis result stored in the first repair analysis result register is transferred to the second repair analysis result register,
the test controller generates information for test completion, and
the output unit outputs the pass/fail flag stored in the second pass/fail flag register and the repair analysis result stored in the second repair analysis result register after the information for test completion is generated by the test controller.
9. The circuit of claim 8 , further comprising a capture register located between the error detection unit or the repair analyzer and the memory output selector, and configured to store the output data selected by the memory output selector.
10. The circuit of claim 9 , wherein
the plurality of memories comprises some memories having different bit widths from each other, and
the bit comparator masks a bit of the expected output value in such a manner that the bit width of the output data selected by the memory output selector is a maximum bit width of the plurality of memories when the output data is not the maximum bit width.
11. The circuit of claim 7 , further comprising a capture register located between the error detection unit or the repair analyzer and the memory output selector, and configured to store the output data selected by the memory output selector.
12. The circuit of claim 11 , wherein
the plurality of memories comprises some memories having different bit widths from each other, and
the bit comparator masks a bit of the expected output value in such a manner that the bit width of the output data selected by the memory output selector is a maximum bit width of the plurality of memories when the output data is not the maximum bit width.
13. The circuit of claim 7 , wherein
the plurality of memories comprises some memories having different bit widths from each other, and
the bit comparator masks a bit of the expected output value in such a manner that the bit width of the output data selected by the memory output selector is a maximum bit width of the plurality of memories when the output data is not the maximum bit width.
14. The circuit of claim 7 , wherein
each pass/fail flag register stores the pass/fail flag for each memory instance, and
each repair analysis result register stores the repair analysis result for each memory instance.
15. The circuit of claim 7 , wherein the plurality of memories comprises a selector configured to select an input terminal for system or an input terminal for test.