Phase change memory
A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region.
1. A phase change memory, comprising:
a phase change storage element;
a P-type metal-oxide-semiconductor (PMOS) transistor configured to adjust a current delivered to the phase change storage element in response to a control signal; and
a control circuit configured to generate the control signal by charging or discharging a capacitor between a predetermined voltage and a source voltage, wherein the source voltage is provided to a source terminal of the PMOS transistor to thereby limit operation of the PMOS transistor to a linear region;
wherein the predetermined voltage is higher than a ground voltage.
2. The phase change memory of claim 1 ,
wherein the capacitor comprises a first terminal coupled to a control terminal of the PMOS transistor; and
wherein the control circuit comprises a charge/discharge circuit, configured to charge or discharge the capacitor to vary the control signal between the predetermined voltage and the source voltage.
3. The phase change memory of claim 2 , wherein the charge/discharge circuit comprises:
a first current mirror configured to generate a charge current to charge the capacitor;
a second current mirror configured to generate a discharge current to discharge the capacitor; and
a charge/discharge switch configured to couple the capacitor to the first current mirror or the second mirror.
4. The phase change memory as claimed in of claim 3 , wherein the charge/discharge circuit further comprises:
a first digital-to-analog converter configured to generate a charge reference current in response to first digital data;
wherein the first current mirror is configured to generate the charge current in response to the charge reference current.
5. The phase change memory of claim 4 , wherein the charge/discharge circuit further comprises:
a second digital-to-analog converter configured to generate a discharge reference current in response to second digital data;
wherein the second current mirror is configured to generate the discharge current in response to the discharge reference current.
6. A phase change memory, comprising:
a phase change storage element;
an N-type metal-oxide-semiconductor (NMOS) transistor configured to adjust a current delivered to the phase change storage element in response to a control signal; and
a control circuit configured to generate the control signal by charging or discharging a capacitor between a ground voltage and a predetermined voltage to thereby limit operation of the transistor to a linear region;
wherein the predetermined voltage is lower than a source voltage coupled to a source terminal of the NMOS transistor.
7. The phase change memory of claim 6 , wherein:
the capacitor comprises a first terminal coupled to a control terminal of the NMOS transistor; and
the control circuit comprises a charge/discharge circuit configured to charge or discharge the capacitor to vary the control signal between the ground voltage and the predetermined voltage.
8. The phase change memory of claim 7 , wherein the charge/discharge circuit comprises:
a first current mirror configured to generate a charge current to charge the capacitor;
a second current mirror configured to generate a discharge current to discharge the capacitor; and
a charge/discharge switch, configured to couple the capacitor to the first current mirror or the second current mirror.
9. The phase change memory of claim 8 , wherein the charge/discharge circuit further comprises:
a first digital-to-analog converter, configured to generate a charge reference current in response to first digital data;
wherein the first current mirror is configured to generate the charge current in response to the charge reference current.
10. The phase change memory of claim 9 , wherein the charge/discharge circuit further comprises:
a second digital-to-analog converter configured to generate a discharge reference current in response to second digital data:
wherein the second current mirror is configured to generate the discharge current in response to the discharge reference current.