Multiple-bit, digital-to-analog converters and conversion methods
Embodiments include DACs and methods for digital-to-analog conversion. A DAC includes an encoder and a plurality of DAC elements. The encoder maps each of a plurality of bits of a digital input value to one of the DAC elements, and produces a sign indication indicating whether a magnitude of the digital input value is above or below a threshold. Each DAC element produces a DAC element analog output signal that indicates whether a received sign indication and a received bit corresponds to a first state, a second state or a third state (e.g., a zero, positive or negative state). In an embodiment, the DAC uses positive historic mapping information when the magnitude of the digital input value is above the threshold, and negative historic mapping information when the magnitude of the digital input value is below the threshold. DAC elements may be configurable into a Return-to-Zero or a Non-Return-to-Zero mode.
1. A digital-to-analog converter (DAC) comprising:
an encoder configured to perform a mapping operation to map each of a plurality of bits of a digital input value to one of a plurality of DAC elements, and to produce a sign indication that indicates whether a magnitude of the digital input value is above or below a threshold; and
the plurality of DAC elements, operatively coupled to the encoder, wherein each DAC element of the plurality of DAC elements receives the sign indication and a bit of the plurality of bits from the encoder, and each DAC element produces a DAC element analog output signal that indicates whether a received sign indication and a received bit corresponds to a first state, a second state or a third state.
2. The DAC of claim 1 , wherein the DAC further comprises:
positive history data storage configured to store positive historic mapping information for positively-signed digital input values; and
negative history data storage configured to store negative historic mapping information for negatively-signed digital input values, and
wherein the encoder is configured to access and use the positive historic mapping information during the mapping operation when the magnitude of the digital input value is above the threshold, and the encoder is configured to access and use the negative historic mapping information during the mapping operation when the magnitude of the digital input value is below the threshold.
3. The DAC of claim 1 , wherein the digital input value is a thermometer-encoded value, and the encoder comprises:
a thermometer code converter configured to convert the thermometer-encoded value by pairing together symmetrically opposite bits of the thermometer-encoded value and performing equivalence operations on each pair to produce a converted thermometer-encoded value.
4. The DAC of claim 3 , wherein the thermometer code converter comprises:
a plurality of XNOR gates, each configured to receive a pair of bits of the thermometer-encoded value and to perform an equivalence operation on the pair of bits.
5. The DAC of claim 1 , wherein the encoder comprises:
a sign determination element configured to produce the sign indication based on a value of a central bit of the digital input value.
6. The DAC of claim 1 , wherein a DAC element of the plurality of DAC elements comprises:
circuitry configured to make a determination of whether the received sign indication and the received bit corresponds to the first state, the second state or the third state, and to produce switch control signals according to the determination; and
a switching network configured to route currents in response to the switch control signals in order to affect the DAC element analog output signal.
7. The DAC of claim 6 , wherein:
when the circuitry makes a determination that the received sign indication and the received bit corresponds to the first state, the circuitry is configured to produce first switch control signals that cause the switching network to route currents away from a signal path of the DAC;
when the circuitry makes a determination that the received sign indication and the received bit corresponds to the second state, the circuitry is configured to produce second switch control signals that cause the DAC to produce a positively-valued DAC element analog output signal; and
when the circuitry makes a determination that the received sign indication and the received bit corresponds to the first state, the circuitry is configured to produce third switch control signals that cause the DAC to produce a negatively-valued DAC element analog output signal.
8. The DAC of claim 6 , wherein the first state corresponds to a zero (Z) state, the second state corresponds to a positive (P) state, and the third state corresponds to a negative (N) state, and wherein:
the DAC element is configurable into a Return-to-Zero (RZ) mode or a Non-Return-to-Zero (NRZ) mode, and
when configured in the RZ mode, transitions directly between the P state and the N state are not permitted to occur, and
when configured in the NRZ mode, transitions directly between the P state and the N state are permitted to occur.
9. The DAC of claim 6 , wherein the circuitry is configured to produce the switch control signals that cause switches of the switching network to change states in a make-before-break manner.
10. The DAC of claim 1 , wherein the first state corresponds to a zero (Z) state, the second state corresponds to a positive (P) state, and the third state corresponds to a negative (N) state, and for any given clock cycle, the plurality DAC elements never include a DAC element in the P state simultaneously with a DAC element in the N state, and either:
are all in the Z state,
are all in the P state,
are all in the N state,
are all in the Z state or the P state, or
are all in the Z state or the N state.
11. The DAC of claim 1 , further comprising a summing junction, operatively coupled to the plurality of DAC elements, and configured to combine DAC element analog output signals from the plurality of DAC elements to produce an analog output signal of the DAC.
12. A digital-to-analog converter (DAC) configured to convert digital input values into an analog output signal, the DAC comprising:
positive history data storage configured to store positive historic mapping information for positively-signed digital input values;
negative history data storage configured to store negative historic mapping information for negatively-signed digital input values;
an encoder, operatively coupled to the positive history data storage and to the negative history data storage, and configured to determine whether a magnitude of a digital input value is above or below a threshold, and to perform a mapping operation to map each of a plurality of bits of the digital input value to one of a plurality of DAC elements, wherein the encoder is configured to access and use the positive historic mapping information during the mapping operation when the magnitude of the digital input value is above the threshold, and the encoder is configured to access and use the negative historic mapping information during the mapping operation when the magnitude of the digital input value is below the threshold; and
the plurality of DAC elements, operatively coupled to the encoder, wherein each DAC element of the plurality of DAC elements is configured to receive a bit of the plurality of bits from the encoder and an indication of whether the magnitude is above or below the threshold, and wherein each DAC element is further configured to produce a DAC element analog output signal based on whether a received indication and a received bit corresponds to a zero (Z) state, a positive (P) state or a negative (N) state.
13. The DAC of claim 12 , wherein the digital input value is a thermometer-encoded value, and the encoder comprises:
a thermometer code converter configured to convert the thermometer-encoded value by pairing together symmetrically opposite bits of the thermometer-encoded value and performing equivalence operations on each pair to produce a converted thermometer-encoded value.
14. The DAC of claim 12 , wherein a DAC element of the plurality of DAC elements comprises:
circuitry configured to make the determination of whether the received indication and the received bit corresponds to the Z state, the P state or the N state, and to produce switch control signals according to the determination; and
a switching network configured to route currents in response to the switch control signals in order to affect the DAC element analog output signal.
15. The DAC of claim 14 , wherein the circuitry is configured to produce the switch control signals that cause switches of the switching network to change states in a make-before-break manner.
16. The DAC of claim 12 , wherein for any given clock cycle, the plurality DAC elements will not produce a positive DAC element analog output signal and a negative DAC element analog output signal simultaneously.
17. A method for performing digital-to-analog conversion performed by a digital-to-analog converter (DAC), the method comprising the steps of:
receiving a digital input value;
determining whether a magnitude of the digital input value is above or below a threshold;
when the magnitude of the digital input value is above the threshold, performing a mapping operation to map each of a plurality of bits of the digital input value to one of a plurality of DAC elements using positive historic mapping information;
when the magnitude of the digital input value is below the threshold, performing the mapping operation to map each of the plurality of bits of the digital input value to one of the plurality of DAC elements using negative historic mapping information; and
each of the plurality of DAC elements producing a DAC element analog output signal based on whether the magnitude of the digital input value is above or below the threshold, and based on a magnitude of a bit received in response to the mapping operation.
18. The method of claim 17 , wherein the digital input value is a thermometer-encoded value, and wherein the method further comprises, prior to the mapping operation:
converting the thermometer-encoded value into a converted thermometer-encoded value by pairing together symmetrically opposite bits of the thermometer-encoded value and performing equivalence operations on each pair to produce the converted thermometer-encoded value.
19. The method of claim 17 , wherein, for each DAC element, producing the DAC element analog output signal comprises:
when a bit mapped to the DAC has a zero magnitude, producing a zero-valued DAC element analog output signal by routing currents away from a signal path;
when a bit mapped to the DAC has a non-zero magnitude and the magnitude of the digital input value is above the threshold, producing a positive-valued DAC element analog output signal; and
when a bit mapped to the DAC has a non-zero magnitude and the magnitude of the digital input value is below the threshold, producing a negative-valued DAC element analog output signal.
20. The method of claim 17 , further comprising combining DAC element analog output signals from the plurality of DAC elements to produce an analog output signal of the DAC.